- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi all,
I've just create a new project in QuartusII tool, following these steps: 1) I opened the 'New Project Wizard' window:- Name of the working directory
- Name of the project
- Select device type
- error (10481): vhdl use clause error at testbench.vhd(20): design library "work" does not contain primary unit "log_package"
- error (10800): vhdl error at testbench.vhd(20): selected name in use clause is not an expanded name
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
you havent included the vhd file with the log_package definition in it.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yeah, in fact that was the problem; these are the libraries I used:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.log_package.all; use work.clock_sim_package.all; use work.reset_sim_package.all; use work.utils_package.all; use work.clkdiv_package.all; So I added (Project->Add/Remove) all the VHDL files I used (log_pachage.vhd, clock_sim_package.vhd, ...and so on) But in log_package: library ieee; use ieee.std_logic_textio.all; library std; use std.textio.all; library work; use work.bus_control_package.all; Now QuartusII get me a new error message:- error (10481): vhdl use clause error at log_package.vhd(18): design library "ieee" does not contain primary unit "std_logic_textio"
- error (10800): vhdl error at log_package.vhd(18): selected name in use clause is not an expanded name
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I get the feeling log package is a debug package not meant for synthesis. Remove log package and any files that use it. (or only use it without synthesis translate on/off pragmas)
std_logic_textio is for outputting std_logic/vectors to text files, just like std.textio. Because they have no meaning for synthesis, quartus does not keep a copy. modelsim has it.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
If I remove 'log_package.vhd', it sends me the error:
error (10481): vhdl use clause error at testbench.vhd(21): design library "work" does not contain primary unit "log_package"- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
then remove the files that use log package, they are probably testbenches and not for synthesis.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
My top VHDL file ('testbench.vhd') uses log_package.vhd :)
I can't remove it, otherwise there's that error.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
then clearly, as a testbench, it is not appropriate for synthesis and should not be compiled with quartus, you are only meant to simulate it in a simulator (such as modelsim).
You cannot compile log package in quartus, or any files that use it. you will either have to make another top level file with connections to pins on your chip, or if the testbench does that (which it should not) put these comments around log_package and anything in the code that uses log_package.
--synthesis translate_off
..anything here is ignored by the compiler
use work.log_package.all;
--synthesis translate_on
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ok, so i tried to compilate the entity and not the testbench;
I added the entity with architectures and libraries: library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.stdma_avalon_package.all;
use work.hdlc_tx_package.all;
use work.hdlc_rx_package.all;
use work.edgedet_package.all;
use work.syncronizer_package.all; and there is this error message: error (10430): vhdl primary unit declaration error at avalon_2oo3_hdlc_entity.vhd(8): primary unit "avalon_2oo3_hdlc" already exists in library "work"
error (10784): hdl error at avalon_2oo3_hdlc.vhd(104): see declaration for object "avalon_2oo3_hdlc"
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Instead of posting every single error here, I suggest 2 things:
1. read the errors and act on them. This one clearly tells you that it is trying to compile two things with the same name. without your code, I cant tell you what the problem is. 2. post the project here.- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page