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I have a problem where I'm telling an output pin to go to a logic low, but it is remaining high. I'm using a Cyclone 4 EP4CE115F29C8.
I'd like the ability to look at the actual value on the output pin from within the FPGA, as well as command it to a certain logic state. This seems like it should be possible based on the Cyclone 4 family datasheet, figure 6-1. Any ideas on troubleshooting this further are welcome...Link Copied
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If it is a normal io pin make it bidirectional (inout). Then you can drive it using for example the debug tool "in system signal source and probes" or a simple toggling bit with an tristate option. The measure the io with for example signaltap...
Check for sure the io routing in the fitter. Then you can be sure your logic was optimized away. You can also do fancy stuff using jtag to force io's but the above methods are easier and faster i think.
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