Number of RUP, RDN pairs for SO-DIMM?

[Altera_Forum]

How many RUP,RDN resistor pairs would need to be connected when using termination calibration blocks for a 64-bit DDR SO-DIMM? I would like to add these resistors to my next board spin but I'm not quite sure whether 1 pair or 2 pairs are needed.  

 Based on the Arria II GX Dev. Kit, it looks like a single RUP/RDN pair is sufficient.  Also, does it matter in which bank the RUP/RDN resistor pair is connected to?  Thanks.

[Altera_Forum]

In the Arria II GX specs doc it states that only one calibration block is needed as long as all of the blocks being calibrated have the same VCCIO. We have an Arria II GX board with 4 discrete DDR2 chips and we only needed 1 set of RUP RDN resistors. 

 From page 6-26:    --- Quote Start ---  You can configure I/O banks to receive calibrated codes from any OCT calibration block with the same VCCIO. All I/O banks with the same VCCIO can share one OCT calibration block, even if that particular I/O bank has an OCT calibration block.  --- Quote End ---  

[Altera_Forum]

Thanks, then 1 RUP/RDN pair is sufficient for my design. 

 One more thing; what is the calibration block actually doing? Automatically tuning the termination resistor to get as close to 50 ohm termination as possible regardless of PVT?   I'm considering the option of using non-calibrated 50 ohm serial termination for my 200 MHz DDR interface. What are the practical implications of non-calibrated vs calibrated serial termination at these low speeds? I have a feeling non-calibrated would work just fine but would love to get some input on the matter.  Thanks.

[Altera_Forum]

I believe the calibration block does what you stated below. I am not an expert in this. I spent tons of time trying to understand all of this when I did my board layout. Now that it is done and working, I don't remember the details. :-) 

 As far as calibrated vs non-calibrated, is there a reason why you do not want to use the 50 ohm with calibration?  If you have access to a simulation tool, you can run a simulation using the DDR model and see what margins you can tolerate. The slower clock means that you can tolerate some ringing due to Z mismatch, but... depending on your signal Tr and Tf and your trace lengths, the ringing, while it may not cause data errors, it may reduce your MTBF because of specs violations.  So, regardless of clock speed, make sure your impedances are matched - a simulation tool helps tremendously here.

[Altera_Forum]

--- Quote Start ---  As far as calibrated vs non-calibrated, is there a reason why you do not want to use the 50 ohm with calibration?  --- Quote End ---    I forgot to design in the RUP/RDN resistors in my current design and would need to make modifications to it. I don't like to make unneccesary changes so if the calibration is not needed then, perhaps, I could leave the resistors out.    --- Quote Start ---  If you have access to a simulation tool, you can run a simulation using the DDR model and see what margins you can tolerate. The slower clock means that you can tolerate some ringing due to Z mismatch, but... depending on your signal Tr and Tf and your trace lengths, the ringing, while it may not cause data errors, it may reduce your MTBF because of specs violations.  So, regardless of clock speed, make sure your impedances are matched - a simulation tool helps tremendously here.  --- Quote End ---    In my experience, the termination impedance can vary quite a lot without affecting real-life signal integrity significantly. I have done SI simulations with Hyperlynx and a +/- 20% impedance mismatch in transmission lines or termination resistors is ok. What I don't know, however, is how much improvement the calibrated termination is compared to un-calibrated.  I guess I'll just design in the resistors, just to be safe!  Thanks.