set_output_delay -max -ve?

[Altera_Forum]

Before I start, I have read rsycs great document and thank you rsyc, it has been a great help. I struggle with I/O concepts most of all mainly because every now and then I have to re-visit source synchronous interfaces - a nightmare at the moment. Then I forget everything for a year or two until the next crisis. Not good. So this time I'm determined to get my brain around it. 

 In Altera AN433, set_output_delay can have a -ve value for -max delay depending on the approach taken for source synchronous outputs. In fact they recommend this approach - so called "maximum data invalid method"  Whilst I can understand that an external delay may be negative i.e. data arrives before clock at destination, why is max <0 and min > 0 in this case? This seems unnatural especially when all explanations I have seen on set_output/input_delay simply say that they describe the external delays. The only clue I have is that -max is for set-up checks and -min is for hold checks.

[Altera_Forum]

FYI, I'm working on a companion source-synchronous document, and hope to have it near completion by the end of the week, if you can wait?

[Altera_Forum]

That's great, I can wait but I can't wait if you see what I mean ;-) 

 The Altera doc (AN433) is very hard to wade through. I think a thorough explanation of set_input_delay and set_output_delay and all the possible values of -max and -min is what is missing from that app note because a proper understanding of source synchronous I/O can't be had without it. The TimeQuest manual doesn't give a proper explanation of this either in my view.  Thanks.

[Altera_Forum]

I agree on both points. (I would still like to disect I/O some more after this.) Remember that the setup check on an I/O really only has two numbers, your setup relationship and the -max value. The setup relationship is what the interface needs to meet timing, and the -max value is how much of this is used externally. Whatever isn't used externally is allowed for the FPGA. So if your setup relationship is 4ns and the -max is 1.5, that means the FPGA has 2.5 to work. 

Conversely, the hold has a similar scenario, where there is a hold relationship and the -min value. If your hold relationship is 0 and the -min value is -1 then the FPGA has +1 to play with. (Hold is always more difficult to understand, but it's basically that your minimum source clock delay + data path gets to the latch register after your longest destination clock delay. I'm simplifying here.) I didn't see in AN433 where the -max is negative and -min is positive, but if that is occuring, could see how it's confusing. I believe this is possible, but not a fan and think it can be accomplished in better ways.  Let's take a simple case(not source-synchronous) of an output port driving another device. Say the clock is 10ns, and hence the setup relationship is 10ns and the hold relationship is 0ns. If the external delays were both 0, then the FPGA would need to get its data out sometime between 0 and 10ns. Now let's say the external device doesn't latch the data for another clock cycle, i.e. at 20ns. You could say the external -max delay is -10ns, which essentially buys 10ns for your setup analysis. Let's also say the external device only latches a cycle before new data is sent, i.e. if your FPGA got its delay out in -10ns would there be a violation. This can be done by saying the -min delay is 10ns. So the -max is -10ns and the -min is 10ns and says the FPGA can get its data out between -10ns and +20ns. Technically, it works. I confused myself twice though. I think it's much easier to apply multicycles to make the setup relationship 20ns and hold relationship -10ns. Then your external delays can be 0ns(or more exactly, your -max will be positive and the hold will be negative). That's one of the issues with I/O timing, and source synchronous interfaces. There are 2 values used to constrain the I/O, the setup relationship and -max value. (And 2 values for hold analysis). So a setup relationship of 10 and -max external delay of 3 will constrian the FPGA as a setup relationship of 7 and a -max external delay of 0, or a setup relationship of 5 and -max external delay of -2.  The problem with source synchronous interfaces is that external devices will spec the exact same thing in different ways. Some will say they phase-shift the clock, for example, while others will say they don't, but they'll givea Tsu/Th that looks like phase-shift. I hope to go through all this at some point. Anyway, I'm babbling. Hope it helps.

[Altera_Forum]

Still babbling... 

Another way to think about the -max and -min external delays is they generally cut into your margin, i.e. the larger the -max value is, the more it cuts into your setup relationship. The smaller -min is, the more it cuts into your hold relationship. That usually makes sense. The -max value becomes negative if you're trying to say there is more margin then the setup relationship, and the -min value goes positive if you're saying there is more margin than the default hold relationship. There's usually about four different ways to think about these things.

[Altera_Forum]

I'd like to get my hands on Rysc's new document when it becomes available. Will you please post a link in this thread?

[Altera_Forum]

Will do. (I will probably start a new thread with a link to it too...)

[Altera_Forum]

Thanks for you comments, all really helpful.  

The bit in AN433 is on page 24: "Altera recommends constraining the maximum data invalid time instead of the minimum data valid time. To constrain the maximum data invalid time, you must set up the output minimum delay and output maximum delay constraints. The output minimum delay constraint value is the positive skew requirement, and the output maximum delay constraint is the negative skew requirement."

[Altera_Forum]

Ugh. Had the document near completion last night and realized it's just not organized correctly, making some issues more confusing than they need to be. Will be delayed a few days to re-work. 

I haven't looked at the AN directly that you quoted above, but it really depends on the definition of skew for a source-synchronous interface(and I don't know if there is one). I generally take the data delay to be the positive number, so a skew of 1ns means the data delay is 1ns longer than the clock, whereas a skew of -1ns means it is 1ns shorter. I've tried to explicitly state "the data delay skewed in relation to the clock delay". I'd be curious if a) you agree with that usage and b) if the wording makes sense. (I've seen other datasheets that just say skew but don't define it. If it's symmetric, i.e. +/-1ns, that's fine since both definitions come to the same conclusion, but often you have to go to their waveforms to decipher the meaning...)

[Altera_Forum]

Yes I agree with your definition of skew and data delay. 

The max and min delay could of course both be -ve or +ve.

[Altera_Forum]

Regarding the actual meaning of set_input_delay & set_output_delay: 

 When I first knew about them from AN433, I was totally confused and it didn't make sense at all if I interpreted them as delay to be inserted inside fpga. The name of these commands does convey that message "set input delay, set output delay". Moreover the help menu vindicated that it is delay with respect to clock.  Looking at the equations of both, I came to firm conclusion that they mean something else. My conclusion on set_input_delay was that we are giving info to compiler about data relation to clock at input pins of fpga rather than asking it to insert those delays.  My conclusion on set_output_delay stayed vague for months. The mystery was solved by looking somewhere else: At Actel SDC documents and I am sure they follow the same standards set by Synopsys.  In Actel document, the definitions are crystal clear: set_input_delay is indeed about telling the compiler the expected delay of incoming data with respect to incoming clock.  set_output_delay is about asking the compiler to put data before the clock edge by value of delay. Now I understand why max delay = tsu and min delay = -tH (ignoring trace delays). Thanks to Actel.  With respect to Rysc's explanations, I am afraid it is not right to assume the two parameters of setup relationship and max delay in the way he describes them. setup relationship is used by altera to mean which clock edges are taken as lauch/latch pairs for setup checks. AN433 clears states and I quote about set_output_delay "It defines the setup relationship with the destination register.  I believe strongly that Altera docs on TimeQuest are a complete mess and making fuss out of trivial differences of actual results from compiler.