Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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small number of timing failures

Altera_Forum
Honored Contributor II
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Probably a stupid question but is there a reason why Quartus cannot tweak the design slighty when only a handful of paths fail to meet timing by a very small amount? 

 

e.g. my design fails to meet hold timing on one path by 10pS or so on the fast 0 degC corner. Why can't this be easily fixed expecially if I'm not using much logic resource and given that I have plenty of setup slack?
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Altera_Forum
Honored Contributor II
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Its probably because Quartus cant identify mulitcycle setups by itself unless you specify. So it just leaves the path alone and lets the the user decide on it. Not sure though. 

 

I have one question: 

 

I think I know when to use "set multicycle path" and "set false path", I want to clarify it with someone. When do you use them? 

 

Thanks, 

AA
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Altera_Forum
Honored Contributor II
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Altera_Forum
Honored Contributor II
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Thanks!! If you have any other resource [Pin Planner, Mega wizard, component Editor, Signal Tap, Power Play] which are not in the Altera Websiste, it will be helpful if you can post it in this thread [or mail it to adityaa@comcast.net]

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Altera_Forum
Honored Contributor II
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de-em, on your original question: 

1) When the design fails a little bit on setup, it really can't do much more. It has basically placed to the point where it doesn't see any moves that would help timing. The only thing that would help is by ripping up tons of logic and starting over(which may help and may hurt). Basically it is running a different seed. So for setup, the answer is no. 

2) For hold, it should be able to do this. Note that hold timing is met in the router by adding delay(the place won't ever place things further apart). First make sure Assignments -> Settings -> Fitter -> Optimize Hold Timing is set to All Paths and the Optimize Mulit-Corner option is checked. Without these, the router won't try to optimize these paths and it will naturally fail. These used to not be on by default but should but are now.
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Altera_Forum
Honored Contributor II
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Just to clarify, the all paths optimization that Rysc refers to above is on by default, but the optimization of all corners is off by default. Turning on that option increases compile time significantly (10-20% likely). 

 

That option may be defaulted to on in the future, but not in QII 11.1 or earlier releases.
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