Who wins VERILOG_MACRO.qsf or `define.v?

[Altera_Forum]

I have a design which `includes a header file which has `defines for default mode, say:`define ASIC_VERSION 32'h00000001 

 I have an "override" in my .qsf to specify the FPGA build, say:set_global_assignment -name VERILOG_MACRO "ASIC_REVISION=32'h12345678"   However, when I map I get this warning:Warning (10886): Verilog HDL macro warning at ...defines.v(line): overriding existing definition for macro "ASIC_VERSION",  The `include file is overriding the .qsf! This is precisely the opposite of my intention. Is there any modifier to make sure that the .qsf file wins?  Thanks, Tom

[Altera_Forum]

Turns out it is load order - just like Verilog. You have to place your VERILOG_MACROs after your VERILOG_FILEs for it to win. ~Tom

[Altera_Forum]

I declared victory too soon - seems to fail randomly, irregardless of load-order.

[Altera_Forum]

How about: 

 `ifndef ASIC_VERSION `define ASIC_VERSION 32'h00000001 `endif  will define ASIC_VERSION only if it is not currently defined (by the .qsf file)  ( replaced `ifdef ... `else with `ifndef )

[Altera_Forum]

Tried that - it did not work. I tried both load orders - fails same.

[Altera_Forum]

Did you modify the definition in the include file to surround it with the `ifndef ... `endif lines? 

 What is the failure you are seeing?

[Altera_Forum]

I did indeed try the ifndef guard around the Verilog `defines - fails same regardless of load order. 

 Failure is the Warning (10886) cited above and the fact that I want the .qsf VERILOG_MACRO definitions to win - not the Verilog.   Strangely, in the .flow.rpt it shows the definitions I want. I get the warnings and then in the actual implementation I see that Verilog won out.

[Altera_Forum]

Update: --verilog_macro= on quartus_map command-line fails same.

[Altera_Forum]

Final word from tech support: "It ain't possible." http://quartushelp.altera.com/current/#msgs/msgs/wvrfx_veri_macro_redefinition_qsf.htm