Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20705 Discussions

2 stages boot loader

Altera_Forum
Honored Contributor II
‎07-21-2011 11:26 AM
1,084 Views

Hi  

 

I'm trying to fit a design that requires a boot loader into a small FPGA, but there is not enough space for both of them. 

 

so I had an idea, why not use 2 designs: 

boot loader design fills up the external RAM, and tells the host when it is done. 

then the host override the boot loader design and loads the "operational" design. 

the operational design NIOS has the external RAM for reset and exception vectors. 

 

before I dive into it and push around the SW team, I would appreciate everyone thoughts and ideas for possible mines, draw backs and better alternatives. 

 

thanks in advance
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎07-21-2011 12:30 PM
353 Views

Do you use SRAM or SDRAM? 

If SDRAM, does it have Auto-refresh? 

If not, there's a risk your contents might get corrupted during reconfiguration. 

What time would reconfiguration take?
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎07-21-2011 01:29 PM
353 Views

Hi 

 

luckily I'm using SRAM. so I don't have to worry about refresh cycles and so on.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.