Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Fmax about Dsp Builder

Altera_Forum
Honored Contributor II
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hello! 

I use dsp builder create a DDS project. But I use quartus II compile it, I get a critical warning(require time is 100M , the actual time is 77.7M ). How can do solve the problem? 

thank you very much!
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Altera_Forum
Honored Contributor II
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I would say you need to pipeline your design better to meet the timing requirements. Use TimeQuest to analyze where your design is failing and add some register in this path.

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