- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I am just started using verilog a week ago and I dont understand how to solve this problem
D:/Quatus files/Megablock_v2/divi_f32.v(230): Instantiation of 'altsyncram' failed. The design unit was not found. I dont understand why I am getting this error when I try to use the division megafunctions on ModelSim. It did not require any addition verilog files to ensure the simulation works. I dont know where to find the design unit and how to add it. Thank youLink Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
Try changing the path of your project since the current has blank spaces: Change: D:/Quatus files/... To: D:/Quatus_files/... Hope this helps you...
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page