Need Help with FFT code

[Altera_Forum]

Hi, 

 I am trying to implement a FFT code on the altera DE1 board. I have some doubts regarding the procedure.  1.Can i simulate the outputs of the FFT in Quartus 11??If so,Can you provide me the link to the manual which will help me do so??  2.Can i use the same code which i have used for simulation for synthesis?  Please help me with these.It'll be of great help.:)

[Altera_Forum]

You need to decide which design metodology you want to use. 

As example: schematic design; verilog HDL code; VHDL code. In every case you can simulate using a testbench and Modelsim (incleded in QurtusII suite).  In every case the simulation environment (testbench) cannot be implemented on the board.

[Altera_Forum]

Like nplttr (http://www.alteraforum.com/forum/member.php?u=31357) said 

The simulation model is created by the FFT generator, in case of VHDL, you should use the vho file for simulation and the vhd for synthesis.

[Altera_Forum]

I am using VHDL code to implement it. 

I have been able to come up with a code for implementing a 4-pt FFT,but the problem is i am not understanding what to do further. Like how to simulate the outputs and test the results? And also how to program the FPGA with this code?

[Altera_Forum]

In any dsp module testing is same, you get stimulus input then its reference output from a software tool e.g. Matlab then pass same input to your module and check outputs for errors. You need a testbench to read stimulus file and ref file then compare. 

For fft use Matlab fft, just one statement: y = fft(x,64);  however you need care to get frame boundaries (64 data frame) correct between Matlab and module. You also need match scaling issue and fft centre(dc centred or not)

[Altera_Forum]

So how do i give the reference inputs in Quartus 11.0? 

 I have been able to get the outputs using matlab but i am not understanding how to simulate the file in Quartus 11.0?

[Altera_Forum]

You need to create text file in Matlab for your input and one for your ref outputs then let the testbench read them. You may already have testbench generated by your tool (ip core) then all you might need is point to those files.