Hello all,
I would like to get some feedback regarding a constraint I am considering applying to my design. Here is a quick description:
I have a statemachine operating at 50Mhz. This statemachine
is creating an external interface (both an external clock and data).
The relationship of these signal is fixed by the statemachine.
Not that it matters but the external clock frequency is approc 300Khz (really slow). The clock is centered aligned to data.
Both clock and data exit the FPGA and terminate into a 74XXX245 buffer
(async).
My question is how to constrain this external clock and data. Given the
speed I was inclined to ignore these, but still I feel they should be addressed.
Based on what I read it would appear that the most relevant constraint
would be the SET_MAX_SKEW. This would at least maintain the clock
and data relationship to the edge of the FPGA. Is this a correct statement?
Also It seems like you would want to specify max_skew from the output
of the registers (pins) to the ports at the top level.
Lastly is the specification for .5 from Rsyncs guide absolute in terms
ns? i.e. .5ns?
Thanks,
jta1
