Why is Altera force-feeding us with Verilog?

[Altera_Forum]

Altera definitely (?) is using Verilog (and System Verilog) to build their latest IP. That's fine by me, after all it is IP and most users don't want to see the internals anyway.  

But the accompanying examples are also made in Verilog and if the user prefers a VHDL output Altera runs it through a 'converter' that produces the worst readable VHDL code I have ever seen. (I compared the .v and .vhd files for the ddr2_example_driver.) The vhdl translator even produces 'deprecated' code :library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  and things like this: addr_value <= A_EXT (A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((test_incomplete_writes_mode AND write_req) AND NOT full_burst_on))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000100"), std_logic_vector'("00000000000000000000000000000010")), 5);  What the hell does A_WE_stdLogicVector do? I know I can find it in the library altera; use altera.altera_europa_support_lib.all; but I just dare not go down there, it certainly won't get any prettier ...

[Altera_Forum]

Generated code, from just about anywhere, is pretty poor. I am a bit dissapointed with non-standard VHDL though. It was probably provided by an external contractor (as I think they produce most of the IP).  

 How about raising a support request? You wont achieve alot ranting about it on this forum.

[Altera_Forum]

--- Quote Start ---  Generated code, from just about anywhere, is pretty poor. I am a bit dissapointed with non-standard VHDL though. It was probably provided by an external contractor (as I think they produce most of the IP).   How about raising a support request? You wont achieve alot ranting about it on this forum.  --- Quote End ---   I do not fully agree with the fact that generated code has to be ugly and illegible, but if you start off with something poorly readable it won't get any prettier translating it.  Looks like they assign the job to the lowest bidder ...  The SR: I am just a poor boy (one of the 80% of the customer base only generating 20% of the revenue) ... and I really don't think Altera will answer anything else than a polite 'this is the way things go down'. I just wanted to get this off my chest. I started using AHDL back in '93 (coming from PALASM and Abel). At some point it looked like Altera was going to switch to VHDL, and we finally went along. Now they have switched to this other language and are orphaning the VHDL user. So I'll just have to learn to read Verilog and its siblings (better than I do now). You never know, but I might even start liking it:)

[Altera_Forum]

Im sure im in the 80% category too, and they're usually prompt getting back to me.

[Altera_Forum]

The only "nice" way would be to write the examples twice. This can get really expensive(not just time writing both, but time spent debugging the two, ensuring equivalency, hiring engineers who are good at both, etc.) It's an ugly problem for IP development. I know it's painful to you and that doesn't help, just mentioning for some sympathy.

[Altera_Forum]

i think the memory controllers (and most of the IP) are developed internally 

 josby: i can sympathize, i recently had to jump from VHDL to Verilog. its not hard at all

[Altera_Forum]

I also did not like verilog ..... 

Today I think the verilog much more practical than the VHDL  (the greatest impose and the developers are required to learn)

[Altera_Forum]

Maintaining dual language generation or writing IP cores in two languages is a huge maintenance burden so that's the reason for the shift to verilog and system verilog. In terms of testing, system verilog offers much more so the only sane choice is to shift to system verilog. VHDL will probably catch up on the test side but by the time they do it might be too late.... 

 To answer the first question of what does that line do..... if I remember correctly that will evaluate to a 1. Again like others have said this is the price paid for having dual language support that is machine generated, it's not pretty and increases the testing burden. (Well) written verilog should be readable by VHDL developers for the most part and visa versa so that's the direction we are moving towards instead of generated code that is difficult to understand.  And before anyone tries to start a VHDL vs verilog war.... don't bother since I'll just lock the thread since it's a waste of forum storage.....

[Altera_Forum]

--- Quote Start ---  To answer the first question of what does that line do.....  --- Quote End ---   Now that was a rhetorical question.    --- Quote Start ---  (Well) written verilog should be readable by VHDL developers  --- Quote End ---   The catch is in 'well written' that well isn't good enough, it must be impeccably written (even for the sake of the Verilog user). Take a look at the DDR2 EXample Driver .v source and you'll see what I mean. I already bought my first Verilog book several months ago, but my workload is high enough to leave no time to experiment. Verilog is not that hard to read and modify, but there are some subtleties like blocking and non-blocking (and a few more?0 I'll have to study.   --- Quote Start ---  Maintaining dual language generation or writing IP cores in two languages is a huge maintenance burden so that's the reason for the shift to verilog and system verilog. In terms of testing, system verilog offers much more so the only sane choice is to shift to system verilog. VHDL will probably catch up on the test side but by the time they do it might be too late....  --- Quote End ---  As I said before, it is perfectly OK to have IP written in Verilog (or any other language). I do not test 'large' systems so I am perfectly OK with VHDL and the internal simulator to test my small building blocks (Avalon ST-like) which can be connected together and operate very predictably. Shifting over to Verilog means to re-write of my VHDL support packages.   --- Quote Start ---  And before anyone tries to start a VHDL vs verilog war  --- Quote End ---   I certainly don't want to start a war ...