Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

dsp builder

Altera_Forum
Honored Contributor II
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hello everyone 

I use dspbuilder design a project. I just want use it design a subsystem. But the signalcompile create a project(including the top level). How can I use dspbuilder create a VHDL files as a component to my project. 

Thank you very much
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Altera_Forum
Honored Contributor II
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in Signal Compiler, use the Export tab to create VHDL for your project

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Altera_Forum
Honored Contributor II
304 Views

 

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My name is Kenvin ! I like chilling out , chatting and having fun! I cant wait to make new friends! I hope everyone will treat me nice 

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me too ! Thank you very much
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Altera_Forum
Honored Contributor II
304 Views

 

--- Quote Start ---  

in Signal Compiler, use the Export tab to create VHDL for your project 

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Thank you very much! I had got it.  

but I have a new problem. I use dspbuilder create a FIR(N=64).But I compile it in quartusII with a error,the device just have 18 dsp block. How can I solve it? If I need design a high order FIR with fpga,how can I deal with it?
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Altera_Forum
Honored Contributor II
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you need to look at things like time division multiplexing/serializing the multiply and accumulate of the filter, or using constant coefficient multiplies in LEs 

 

DSP Builder Advanced Blockset or FIR Compiler II are really good at this sort of thing
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