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Hi,
I am intending to design a PID controller loop in FPGA for monitoring a stable current . I am quite new in the FPGA world so I need help in the following issues: 1) My loop cycle frequency is 75-90 MHz. I believe I would need ADC and DACs since FPGA is a digital system. I was wondeing if there is any Altera FPGA devices that has built-in ADCs and DACs with that high sample rate(my ADC might have to upsample as well). 2. I need a noise rejection of 60 db, is it feasible to realise in FPGA. As a begineer, I am not sure which device family to look at, any help would be appreciated. ThanksLink Copied
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At this stage you would require external ADC/DAC's. Several dev boards have ADC and DACS on them. I would look at any of the DSP development kits as a starting point.
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Hi anakha thanks a lot for your reply. I have looked at the DSP development kits and it seems the prices are out of my budget, and I don't really need some of the other high-performance features like video processing and so on. I was wondering if there is any way I could configure Cyclone III family FPGA with ADC and DACs. Also is there any potential source of noise amplification while using FPGAs? I will be using differential mode signaling but still an estimate would be helpful. Also how many logic emlements I might need in a typical PID loop controller design?
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