PFL with S4 and MAXii

[Altera_Forum]

Hi 

I encounter an issue while using a PFL (FPP) configuration scheme. Actually: -- the Flash memory is correctly seen by the CFI and well programmed -- the configuration has the following behavior:  + it behaves well 2 times out of 10  + it fails with 2 distinguished symptoms:  * the FPP simply does nothing and the FPGA stays non-configured  * the FPP stalls with an error (nSTATUS goes low) -- when the FPP design is kept in reset and released far after the POR, the config process immediately stalls with an error without any DCLK cycles  So my questions are: -- does the PFL/FPP design monitor the nCONFIG and nSTATUS lines prior to launching a cycle? -- is there a safe way of delaying something here in order to make sure? -- is there a sample timing diagram for this feature showing the behavior?  Thanks in advance for your help K.r. Thomas

[Altera_Forum]

The FPP mode requires 2 clocks after the completion of data in order for the device to complete the configuration process. 

 This may be the issue you are seeing. I know it was with our Cyclone III LS design.  Pete

[Altera_Forum]

Hi Pete 

And thank you for your reply. I don't believe that I have this issue cause it happens to work well. In fact, I believe that I have a timing issue somewhere. When I stated that the MAXii PFL design does nothing, I meant that, possibly, it has considered that the S4 simply needs nothing. That was the purpose of my question regarding the sample timing diagram.  I assume that the PFL design monitors the configuration wires and would decide to start or not the cfg cycle. This is my missing info.  I will start to simulate, but I do not know if this would work as the AN states that one can not.....  Regards Thomas

[Altera_Forum]

Hi 

 Actually, the problem is now solved. It was question of delaying the PFL_RESET after S4 and MAXii start up, now it is perfect. If somebody is interested, I can provide (much) more details. Whilst doing so, I saw that the IP does something with the FLASH even when not in reset condition. Unfortunately, this is not well documented and if somebody from ALTERA reads this tread, it would be nice to have a more consistent documentation on this PFL feature and some troubleshooting guidelines. Timing diagrams of coarse, never can get enough of these.  Kind regards Thomas

[Altera_Forum]

Hi,  

  I am having a similar problem with the PFL (FPP) scheme.    I have a Max II act as the configuration controller, which load configuration data from a flash and configure a Stratix IV FPGA.   (All terminologies I use here are according to the Parallel Flash loader userguide.)   I followed the Parallel Flash loader megafunction user guide to create a project for Max II. Currently, I can see that whenever the fpga_nconfig line generates a low pulse, the fpga_nstatus follows with a low pulse, and the fpga_conf_done goes to low. But nothing happens afterwards, I don't see a fpga_dclk being generated by the MAX II. However, I do see the pfl_clk working properly.    I kept the pfl_nreset input to high at all time.   Can you provide more details on how to debug the PFL megafunction, and give me some hint please?  Cheers, Han

[Altera_Forum]

I am happy to report that delaying the nreset signal after the POR fixed my problem too.

[Altera_Forum]

Hi! 

Glad to hear that you made it and sorry for my late reply. I was about to send you my design and schematics as well.  Admittedly, the PFL function is unsufficuiently documented. Too many components coming out of reset at the same time: -- the FPGA (e.g. S4) -- the CPLD itself -- the related flash memory for the storage itself  So starting the whole procedure (a bit) later definitely helps. I have also added LEDs and a pushbutton which would re-trigger a configuration, all is fine.  Have fun Thouthi38

[Altera_Forum]

Hi,  

Thanks for replying!  Actually, I wonder if you could still send me your design and schematic. I used a board from Hitechglobal, and I am having a little trouble to implement the re-trigger configuration for PFL.  Cheers, Han

[Altera_Forum]

Hi 

I can for sure, at least the project archive for Quartus 10.1 SP1 and related extracts from schematics in PDF Please provide your email address as I can not put files here.  Kind regards Thomas

[Altera_Forum]

Hi,  

Thanks, my email is hw342 at cornell dot edu.