Best way for a 3d matrix

[Altera_Forum]

Hi, I need to use a matrix of 8x8, wich each position have a 8bits number. Something like 8x8x8. 

I would like to know how can i do that. I actually did a test project using the following method:  TYPE array1 IS ARRAY (0 TO 7, 0 TO 7, 0 TO 7) OF STD_LOGIC; SIGNAL matrix: array1;  It compiles fine and seems to work, but when I simulate, I get unknown values in every position.   For example, I have a 2x2x2 matrix input and a 2x2x2 matrix output. And I assign every position of the input to the same position to the output. On the simulator, I get all outputs as unknown, not the actuall 0 or 1.  Is this the best way to declare a 3d matrix? If so, how can I fix the simulator?  Thank You!!

[Altera_Forum]

First of all, the 'U' value will be because you havent initialised your signals or assigned them to anything. Do you have a testbench? can you post your code? 

 Secondly I would never declare a multidimensional array of std_logic. It makes life very difficult, unless you enjoy assigning individiul bits of a whole number.  What are these value meant to represent? numbers? just an array of bits?   Anyway, easiest to do something like this:  type array1_t is array(0 to 7, 0 to 7) of std_logic_vector(7 downto 0); signal matrix : array1_t;  then you can assign stuff like this: matrix(3,7) <= x"FF";

[Altera_Forum]

Tricky, I really appreciate your help. 

 Here's the code. It's just a small test I'm doing to find the best way to do what I need. All this is suposed to do is send the input(entrada) to the output(saida).  ---------PACKAGE--------- LIBRARY ieee; USE ieee.std_logic_1164.all;  PACKAGE matrizes IS   TYPE array_entrada IS ARRAY (0 TO 3, 0 TO 3, 0 TO 3) OF STD_LOGIC;  TYPE array_saida IS ARRAY (0 TO 3, 0 TO 3, 0 TO 3) OF STD_LOGIC;   END matrizes;   ---------------------- -- MAIN CODE ----------------------  LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.matrizes.all;   ENTITY rct IS PORT ( clk: IN STD_LOGIC; entrada: IN array_entrada; saida: OUT array_saida); END rct;  ARCHITECTURE comportamento OF rct IS  TYPE array1 IS ARRAY (0 TO 3, 0 TO 3, 0 TO 3) OF STD_LOGIC; SIGNAL sinal_entrada: array1;   Begin  PROCESS(CLK)  BEgin  FOR i IN 0 TO 3 LOOP  FOR ii IN 0 TO 3 LOOP  FOR iii IN 0 TO 3 LOOP  sinal_entrada(i,ii, iii)<= entrada(i,ii, iii);  saida(i,ii, iii)<=sinal_entrada(i,ii, iii);  END LOOP;  END LOOP;  END LOOP;  END PRocess; END comportamento;  The numbers represents pixels of an image. I want to work with an 8x8 image, each pixel with 8 bits. Maybe there's some easiest way to do that. This is just what I could think about.  As reference I'm using the book Circuit Design with VHDL - Pedroni.  Thank You!

[Altera_Forum]

Many things wrong with this style of code. 

 1. you have clock in your process sensitivity list but you dont use clock inside the process. This will NOT create registers when you synthesise it, even though it may appear in simulation to be a dual edge flip flop.  2. Usually an image would be stored in ram. With this code, you are just inputting an entire image. What happens when you get to an image that is 1280x720, or similar? all your resources disspear and you only have a limited number of input pins, plus there is no interface that I know of that could get this much data in parrallel into an FPGA.  3. You should never define your own arrays of std_logic, like I said before. There are already some defined arrays of std_logic - std_logic_vector, signed and unsigned. Use those to make life easy for you, dont create your own versions.  4. Personally, with each value as a pixel, I would probably use an integer type or unsigned type.  eg.  type image_t is array (0 to 3, 0 to 3) of integer range 0 to 255;  5. Why have you got 3 different array types that are all basically the same thing. If you had the entrada and saida as the same type, you wouldnt need the loop:   ENTITY rct IS PORT ( clk: IN STD_LOGIC; entrada: IN array_entrada; saida: OUT array_entrada); END rct; ..... process(clk) begin if rising_edge(clk) then saida <= entrada; end if; end process;   6. And finally - stop trying to get ahead of yourself. I suggest you go back to the fundamentals of digital logic before you try and write any more VHDL. If you try and take this any further, you are going to get yourself into a state where if you want code that will actually work on an FPGA, you will have to start all over again.

[Altera_Forum]

First of all, thanks for your time. 

 What I intend to do is a modified version of the DCT.  About the image input, i really doesn't know yet how it will be done and if it will be stored into a memory. I believe serial. This week I have an appointment with my leader and we will decide. But After I have a project that makes the 8x8 compactation, I can always call it in a different project as a component. Like your example, 1280x720, can be decomposed in 14400 8x8 blocks. I will have a project that makes that.  As I said this is only for tests, since I didn't worked with arrays before.  I really have to be able to manipulate the bits of the pixel, since I must use my own adder/subtractor.    --- Quote Start ---  There are already some defined arrays of std_logic - std_logic_vector, signed and unsigned.  --- Quote End ---   Where can I find more info about that?  When I get more data about my project I explain to make it a little bit clear.  Thanks!

[Altera_Forum]

I suggest reading any VHDL tutorial.

[Altera_Forum]

Ok, I'll see if I can find some VHDL tutorial. 

 Just one last help if possible for me to understand why I get this error(i've had this error before).  this following code shouldn't be working? I get an error: "Error (10476): VHDL error at RCT.vhd(74): type of identifier "entrada" does not agree with its usage as "array_saida" type". As far as I understand, entrada and saida is the same type of array.  ---------PACKAGE--------- LIBRARY ieee; USE ieee.std_logic_1164.all;  PACKAGE matrizes IS   TYPE array_entrada IS ARRAY (0 TO 3, 0 TO 3) OF STD_LOGIC_VECTOR(3 downto 0);  TYPE array_saida IS ARRAY (0 TO 3, 0 TO 3) OF STD_LOGIC_VECTOR(3 downto 0);   END matrizes; ------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.matrizes.all;   ENTITY rct IS PORT ( clk: IN STD_LOGIC; entrada: IN array_entrada; saida: OUT array_saida); END rct;  ARCHITECTURE comportamento OF rct IS BEGIN   saida<=entrada;  END comportamento;  Thank You!

[Altera_Forum]

array_entrada and array_saida are not the same type, because you have made them separatly. This is because VHDL has strong typing, when you make 2 types they are not the same. 

 Because they are similar types, you may be able to get away with this:  saida <= array_saida( entrada );  but the best thing to do is just declare saida and entrada as the same type:  port( entrada : in array_entrada; saida : out array_entrada ...  saida <= entrada;

[Altera_Forum]

Ok, I finally understood. 

Thanks.