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hi all;
i have this code for a 5-bits binary counter : LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY counter IS PORT ( count : OUT unsigned (4 DOWNTO 0); load : IN STD_LOGIC; pre :IN unsigned (4 DOWNTO 0); Clk : IN STD_LOGIC); END counter; ARCHITECTURE Behavioral OF counter IS SIGNAL c : unsigned(4 DOWNTO 0) := "00000"; BEGIN count <= c; PROCESS(Clk) BEGIN IF( rising_edge(Clk) ) THEN IF(load = '1') THEN c <= pre; ELSE c <= c + 1; END IF; END IF; END PROCESS; END Behavioral; I want to connect the output to a binary decoder that shows the state of the counter how can i do that? can any one help me plzLink Copied
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Hi,
You have to create a entity that is hierarchically superior, and instantiate this "counter". You may Review VHDL basics since I detect that your teacher is not present yet(I have answered to your old posts)
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