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AHDL, VHDL or Verilog?

Altera_Forum
Honored Contributor II
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Hello everyone,  

I am new with FPGA. 

Now I would like to learn FPGA but confused with AHDL, VHDL and Verilog. 

Could anyone describe what are the difference between them? 

What is your suggestion for me who want to start with FPGA?  

I find out that Verilog is a new one! 

Your replies are fully appreciated!
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Altera_Forum
Honored Contributor II
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AHDL is Altera HDL. Altera is a profit making company that keeps us going as well and runs this forum. They are very good people, believe me except for some of their documentations. 

 

Verilog and vhdl are standardised by IEEE I believe. VHDL is commonly used in Europe but Americans like Verilog more just to be different. So pick your own.
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Altera_Forum
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AHDL is Altera's proprietary language. I would not bother to learn it. 

 

VHDL and Verilog are the primary HDL languages. Learn a little bit about both and use the one you are most comfortable with. 

 

A lot of the newer Altera IP and verification IP is being delivered in SystemVerilog format (the newer-better-Verilog). 

 

I primarily develop with VHDL, but for designs that use Qsys and SOPC Builder I have been using SystemVerilog (to save fighting too much with the Altera Verification IP suite). 

 

Cheers, 

Dave
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Altera_Forum
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Just to give you the flavour: 

VHDL is very tough on type and syntax. Hardly ever I wrote a program(12 years now) without failing first to many syntax errors. Verilog is more friendly, you can write anything and it is always happy.
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Altera_Forum
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AHDL is proprietory and is not supported by anything other than quartus, so no simulation is possible. 

 

VHDL is strongly typed, so many problems can be picked up at compile stage and linting is not really required, but some people seem to find it tough to learn. 

 

Verilog is more C-like, and allows you to get away with more, but can lead to some more annoying debugging.
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Altera_Forum
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VHDL was developed for military purpose. more structured, and verbose. 

 

I think you can be more creative with Verilog. 

 

I would recommend Verilog.
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Altera_Forum
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If I were starting out today, I would use SystemVerilog. Altera has very strong support for it and is improving it with every release, and as someone mentioned, is developing new IP in this language. It is a super-set of Verilog and adds a lot of the structure that VHDL has, but it is optional to use it. IMHO, this is the way of the future of HDL (although we may never be able to fully kill VHDL unfortunately :-)

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Altera_Forum
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Thank you so much guys. 

Now after read your replies, I think I will learn Verilog!
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Altera_Forum
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FYI, there is a new language in development called Bluespec. My question to others: What are the chances of this language becoming as popular/widely used as Verilog.

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Altera_Forum
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I doubt it will have much of an impact, or at least it will take a while to dislodge VHDL or Verilog, as they have such large momentum. 

 

We've had SystemC come along and there are companies that can claim synthesis of systemC, but it hasnt got much traction in the 6 years Ive been coding.
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Altera_Forum
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Thank you tricky

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Altera_Forum
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Is Qsys based on point to point architecture? 

Is SOPC based on bus architecture?
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Altera_Forum
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--- Quote Start ---  

Is Qsys based on point to point architecture? 

Is SOPC based on bus architecture? 

--- Quote End ---  

 

 

Thats getting Off topic - I suggest you start a new thread.
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Altera_Forum
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alright, thanks

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Altera_Forum
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About the emergence of a new HDL language, I'm rather pessimistic. Some fields of the industry are very slow to adapt to new standards. As an example some customers still ask for VHDL'93 and System Verilog, despite it's advantages, isn't as widely used as it should be. 

 

As for emergence of a new HDL that would cover all our needs and solve flaws of both VHDL and Verilog... well it makes me think about that comic: http://xkcd.com/927/ ;)
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Altera_Forum
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i see SystemVerilog picking up pretty well

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Altera_Forum
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--- Quote Start ---  

AHDL is Altera HDL. Altera is a profit making company that keeps us going as well and runs this forum. They are very good people, believe me except for some of their documentations. 

 

Verilog and vhdl are standardised by IEEE I believe. VHDL is commonly used in Europe but Americans like Verilog more just to be different. So pick your own. 

--- Quote End ---  

 

I strongly agree with the supporting documents part
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Altera_Forum
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i was writing in verilog for couple of years. and came to conclusion that your module may work perfectly in one project, and will not in another. i guess the reason lies in the way verilog itself is engineered. my personal opinion is that no language knows how to treat altera's fpga better than AHDL itself. in verilog you model behavior. and god knows what decisions will synthesis make to satisfy that behavior. since verilog throws you far from gate level , sometimes your behavior is too complex or even errorous to synthesize but you don't sense it anymore.because you lost a gate level vision. you have a demand and want it to be satisfied. that's where things get complicated. verilog tries to swallow everything without questioning. that is why in some projects verilog module works perfectly, and in some other projects it does not. sometimes outside of module, you add a very unimportant multiplexer in addition to the output of your module and it starts to synthesize correctly. remove it - again, module is dead.... sometimes very important registers get synthesized away that leads to catastrophic results.in short nobody knows what will come into synthesis's mind when it tries to put your behavioral model into realization. sometimes it does synthesizes correctly. and sometimes logic drives synthesis so far that it starts to dysfunction. ..change a tiny option in quartus from normal fitting to aggressive one(or vice versa), and your module is again dead... i wonder how could such a colossal barrier was left without notice. people continue working with it as with something unavoidable. it's fine when entire project is yours and you can run after single register but nobody will forgive you at work that you gave them some module that sometimes synthesizes and sometimes not. boss demanded this morning to study AHDL. well... if it came to this.. what choice do i have. what decisions did you made in your life in similar situations people..?

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Altera_Forum
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If my company insisted on AHDL, Id find a new job. Its deprecated and altera dont even recommend it. 

No one uses it. Its a dead language. It was written to fit with old technologies, and now that technology has moved on, so features of AHDL dont map directly to the elemtary parts in FPGAs any more. 

 

Basically - forget AHDL - you wont be very employable. It cannot be simulated and cannot be easily ported to Xilinx.
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Altera_Forum
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hmm... iiii... don'tknow! i can simulate AHDL in modelsim same way i do with verilog. or mixed verilog - ahdl project, also simulates perfectly. modelsim needs a netlist of logic gates it does not care about language (i think). and company i work in produces competitive modern hardware on worldwide market. in it, FPGA s (cyclone 4. 115 000 cells) nearly 100% is programmed in AHDL. but i agree that it is an old language and kinda has a prehistoric style synthax :) working with it feels like working with a dinosaur :) and yes it may make me non employable. but trust me if you compare verilog's synthesis stability and AHDL 's synthesis stability, AHDL proved through years that it's synthesis is always correct while verilog may synthesize something away only because the module was copied in a more dense project and compiled. i know you don't believe me but. nobody did before they copied my module. we all had eyes on out foreheads. how is this possible but it is. of course it could be my lack of knowledge and bad coding but i usually run after each register and it's timing. and it worked great on lighter projects where only 20% of fpga was used. as fitter sees that resources are on limits, say close to 90%, the synthesis and fitter simply chews away verilog module parts. again, forgive me if my incompetence makes me say incorrect things... but i am sure many people have observed the same things with verilog. tricky... you are a moderator here so.. your suggestion has a value because you work for altera. so is it true? that altera is planning to withdraw AHDL? that would be a big mistake i think.companies like mine are welded to altera and they can't even look away from it. because of AHDL. xilinx users are also welded to it because of xilinx programming language (i forgot it's name). by withdrawing AHDL altera will simply force people to jump on verilog. which will open their hands -to more freely slide between altera and it's competitors (according to whoever places cheaper prices on better products). you own us guys :D and you are planning to let it go? well i don't know :)))

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Altera_Forum
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I dont work for altera, and altera will never remove AHDL support as it would kill too many legacy products (a and check the /db/ folder when you compile - its full of AHDL primitives). 

 

Yes, you can simulate AHDL with a netlist - but it is a netlist and hence very very slow. We have simulations that take hours to run with just RTL code - I hate to think how long they would take with a netlist. Hence AHDL is of no use to the majority of the design market for FPGA, and utterly usless for ASIC development. We also use both Altera and Xilinx chips where I work - so portability is a primary concern - so no schematics, no AHDL, and HDL must be as portable as possible - so inference is used most of the time. 

 

Most Altera IPs now are done in systemVerilog.  

 

With larger designs, Behavioural code is a blessing, not a curse.
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