Frequency of StratixIV

[Altera_Forum]

Hi, 

 I'am so sorry if there are some mistakes in english. I try to modify the frequency of StratixIV (used the PLL in SOPC builder), always, i obtained with the clock tools the same frequency 100Mhz. I see that's abnormal problem.  Any suggestion please :(.

[Altera_Forum]

Hello Aflouton, 

  Can you post your timing constraints file?(*.sdc file) Does it have the following lines in it: derive_pll_clocks -create_base_clocks? Have you regenerated the SOPC project after you have modified the PLL? Have you recompiled the project after you have modified the PLL in SOPC builder?  Thanks,  Ben

[Altera_Forum]

Hello Protocol Engineer, 

Think you very much for your reply. Of course in regenerated my SOPC in every change. Also the project.  in the pll.sdc there are the two line "derive_pll_clocks -create_base_clocks" but this line is comment. This is the file pll.sdc  # Uncommenting one of the following derive_pll_clocks lines# will instruct the TimeQuest Timing Analyzer to automatically# create derived clocks for all PLL outputs for all PLLs in a# Quartus design. # If the PLL inputs are constrained elsewhere, uncomment the# next line to automatically constrain all PLL output clocks.# derive_pll_clocks # If the PLL inputs are not constrained elsewhere, uncomment# the next line to automatically constrain all PLL input and# output clocks.# derive_pll_clocks -create_base_clocks    Thanks for your helps  

[Altera_Forum]

Hello Aflouton, 

  Do you have any other sdc files that you are using in your project? If not, without including timing constraints in your project, you won't get correct timing analysis. You might try uncommenting the derive_pll_clocks line mentioned before in the pll.sdc file, which will derive the timing constraints from the pll in your SOPC project. You will also need to make sure the sdc file is included in your project(in Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file).  -Ben

[Altera_Forum]

Hello Protocol Enginner, 

 Yes i have other sdc file "CPU.sdc, pll.sdc, and tse_mac_constraints.sdc". There are two line contain derive_pll_clocks. wich line i uncommentig. When i try to go in timeQuest under assignement setting i find two file CPU.sdc and tse_mac_constraints.sdc , and the pll.sdc not included.   Thanks friend, 

[Altera_Forum]

Uncomment the line "derive_pll_clocks -create_base_clocks" in pll.sdc and add in pll.sdc to your project through Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file. Let me know how this works. 

[Altera_Forum]

yes that's i do, uncomment the line derive_pll_clocks -create_base_clocks" and add pll.sdc. Sorry what's the timing file. 

I hope that will work.  think you protocol. 

[Altera_Forum]

The timing filing is the *.sdc file. A better name for it is the timing constraints file, that tells Quartus what frequencies the clocks are, false timing paths and more. Please let me know if that works for you.

[Altera_Forum]

I make as you said. But always i find the same time.  

I explain to you what i do exactly. I have the SOPC given by the stratix IV GX. It work with simple program hello_world, i try to change the software, in the end i puts the execution time of my program. When i make a debug as NIOS II, i obtained 300ms.  Every time i change the frequency, i notes that the time always 300ms.  I change first the frequency under SOPC (input of PLL is 50 MHZ, pll.co=150Mhz, ppl.c1=150 MHZ) and i finished by generate. As you said,i uncomment derive_pll_clocks -create_base_clocks and add the three file "CPU.sdc, pll.sdc, and tse_mac_constraints.sdc" to timing analyser, Finally i compile my project. when i debug my program after building i obtained also 300 ms.

[Altera_Forum]

Can you upload a qar of your project?

[Altera_Forum]

Of course friend, you will find it in attached file. 

 Thanks

[Altera_Forum]

Hi Protocol, 

 Are you understand the problem or no?

[Altera_Forum]

Hey Aflatoun, 

  I believe I understand your problem. You have a program that you are running on your processor. This program takes about the same amount of time whether your system clock is one frequency or a faster frequency. Is this a good explanation of your problem? I looked at your qar and did not find any software. Based on the simplicity of the software, most of the time taken could be initialization of the FPGA and your system rather than time spent running your program. So it is possible that if make your program more complicated, with more loops, that it will take a longer amount of time. Be careful with this approach though, since the software compiler can optimize out what it sees as useless commands. Please let me know if this doesn't help.  Thanks,  Ben

[Altera_Forum]

Hey protocol, 

 Yes you are understand my problem and think you very much for the explanation. my software he will contain only one loops.   Protocol, i constate a new thing that when i try to use the tools RTL View, in the schematic the cpu_clk is related directly to the sys_clk. In the assignement pins the sys_clk is related to PIN_AF34 (50 Mhz), i mean with this if the cpus_clk is always relted to sys_clk, it logic to give me always the same execution time.  Now, but in my SOPC i relate the cpu_clk to the pll.co (100Mhz). It is logic this or no? Do you have any suggestion?

[Altera_Forum]

Could you show a screenshot of your sopc system? Are you sure the Nios CPU is using the correct clock? You should see the pll's output used as a clock in the RTL view. 

How do you measure the execution time? What is the order of magnitude of the execution times you are measuring? What does your loop do? Some actions (ex: i/o) will have an execution time that can be rather independant from the cpu clock.

[Altera_Forum]

--- Quote Start ---  Could you show a screenshot of your sopc system? Are you sure the Nios CPU is using the correct clock? You should see the pll's output used as a clock in the RTL view. How do you measure the execution time? What is the order of magnitude of the execution times you are measuring? What does your loop do? Some actions (ex: i/o) will have an execution time that can be rather independant from the cpu clock.  --- Quote End ---    Of course in the joint file the screenshot of my SOPC system. Of course as mentionned on the screen the NIos CPU is related to the correct clock.  I mentionned this in the back thread, i say that when i try to check in the RTL viewer, i find that clock isn't related to sys_clk(150mhz) from th pll, but it is is related directly to clkin_sys, when i go to check in the assignement menu i find that this pin is related to PIN_AC34. PIN_AC34 is related to an oscillator 50 Mhz as writen in the handbook of this kit.I add a screenschot of RTL to more explain for you.  For measurement time, i measure in the NIOS II software with the instruction clock().  I make exactly as this: start =****(); my code ; end= clock(); I put to your attention that tha instruction clock return tim in tick. I devise by 100 to abtained the execution time in second. For me i need to puts the final in µsecond. I add also my small program in the attached file. My loop will make some arithmetique operation (pow, add, multiplication) and every iteration there are a variable that give the decision to exit the loop or non. The maximum of iteration of the loop is 4. I hope that is clear for you Daixiwen. If you need some information i wil be happy to more explain for you the problem.  Think you

[Altera_Forum]

Your screenshots are extremely hard to read. From what I can decipher in the sopc shot, the CPU clock is 50MHz. Does it show 100MHz in the clock list when you change the setting in the pll component? 

In the RTL view you should find the pll inside the sopc block, several levels down in the hierarchy. You have lots of printf's in your code. This is typically an I/O operation than will take some time, even with a fast CPU. You should have a loop without any I/O between your two clock() calls if you really want to see a difference with a faster clock.

[Altera_Forum]

--- Quote Start ---  Your screenshots are extremely hard to read. From what I can decipher in the sopc shot, the CPU clock is 50MHz. Does it show 100MHz in the clock list when you change the setting in the pll component? In the RTL view you should find the pll inside the sopc block, several levels down in the hierarchy. You have lots of printf's in your code. This is typically an I/O operation than will take some time, even with a fast CPU. You should have a loop without any I/O between your two clock() calls if you really want to see a difference with a faster clock.  --- Quote End ---    Sorry for the quality of the screen. I attached the same screen in compressed folder. How you after you decipher you say that the clock is 50 Mhz, if you see in the new screen, that the cpu clock is related to the sys_clk. And the sys_clk is an output from the pll. Of course he show to me 150 Mhz in the clock list, you can check this from the screen of the SOPC. the PLL output also have as value 150Mhz. In RTl schematic, i find just pll_125, this last don't related to clock CPU.   You have reason about the printf instruction, i note Daixiwen that i don't need for this. I add the printf instruction to see the result and to increase the execution time to appear the difference when i make some modifcation. You know that when i delete the printf instruction always i obtained 0 as execution time. If there are a method to calculte the clock cycle or to appear the execution time in micro-second, really i will be happy to discover :).   Think you Daixiwen

[Altera_Forum]

Yes, from what I see on the screenshots, you should be fine. If you want to find the pll that generates the 150MHz in the rtl viewer, you'll have to go deep into the sopc component. 

If the code you want to test is too fast to get an accurate timing, you have two solutions:[list][*]use a higher resolution timer instead of the system timer (it looks like you have a highres timer in your system) [*]put your code in a big loop. As an example you can execute your code 1000 times, and then divide by 1000 the time you measured. Adjust the number of times you execute your code until you have the required accuracy.

[Altera_Forum]

--- Quote Start ---  Yes, from what I see on the screenshots, you should be fine. If you want to find the pll that generates the 150MHz in the rtl viewer, you'll have to go deep into the sopc component. If the code you want to test is too fast to get an accurate timing, you have two solutions: [list] [*]use a higher resolution timer instead of the system timer (it looks like you have a highres timer in your system) [*]put your code in a big loop. As an example you can execute your code 1000 times, and then divide by 1000 the time you measured. Adjust the number of times you execute your code until you have the required accuracy.  --- Quote End ---    What do you mean go deep into the sopc component? Do you mean i change the option of the component. Think you for the solutions, for the second it's that i used.

[Altera_Forum]

NO I meant in the RTL viewer. What you are seeing is only the top level view. To find the pll you will need to go down the hierarchy by looking inside the SOPC component. You can also try to find it in the tree (tree list on the left of the rtl view).