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Error compiling design Test3S150Board_HSMA.mdl in DSP Builder v8.0

Altera_Forum
Honored Contributor II
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I have installed Quartus version 8.0 and DSP Builder v8.0 that came with the Stratix III DSP Development Kit. DSP Builder v8.0 is being used with Matlab 2010a. In the directory C:/altera/80/quartus/dsp_builder/DesignExamples/Demos/Board/StratixIII_DSPBoard_3S150/Test3S150Board_HSMA.mdl is a Simulink Model using DSP Builder blocks for sending a sine wave from a D/A to A/D port on the HSMC card included with the board. Simulating the model in Simulink will work fine. However, attempting to compile and generate HDL code (Double clicking on SignalCompiler in the model then pressing "Compile") will receive the following error: "Error: Part name EP3SL150F1152C4 is illegal ". I am attempting to generate HDL code that can be downloaded to my Stratix III DSP Development Board.

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Altera_Forum
Honored Contributor II
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I don't have 8.0, but I tried compiling with the design using DSP Builder 11.0 and Quartus 11.0 and had no problems. 

 

If possible you should upgrade to a newer version.
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