Simulate problem about (altfp_sqrt) core

[Altera_Forum]

:confused::confused:In my program I just implement an IP core(altfp_sqrt) by using megawizard. however after simulation by modelsim, the result always shows as high Z. 

Can any body help to solve this problem? Thank you very much!!!   /*****************program********************************/ module sqrt (clk, idin, dout); input [31:0] idin; output [31:0] dout; input clk; wire [31:0] idin; wire [31:0] dout; ddr ddr_sqrt (  .clock(clk),  .data(idin),  .result(dout)  );   always @ (posedge clk)   $display ("dout = ", dout); endmodule   /**************test bench************************************/ module sqrt_tb;  reg clk;  reg [31:0] data;  wire [31:0] idin; // data in  wire [31:0] dout; // data out assign idin = data; always# 10 clk = ~clk;  initial  begin  clk = 0;  data = 'b100;  end sqrt m(clk, idin, dout); endmodule /********************************************************/

[Altera_Forum]

ddr ddr_sqrt ( .clock(clk), .data(idin), .result(dout) );Check that your MegaWizard generated altfp_sqrt module instance is indeed named "ddr".

[Altera_Forum]

thank you . but I checked the altfp_sqrt module name is right. 

And I re-do the whole program, it still has the same problem.

[Altera_Forum]

/***************Top Module ****************/ 

module fp_sqrt (clk, idin, dout); input clk; input [31:0] idin; output [31:0] dout; wire [31:0] idin; wire [31:0] dout; sel_sq fp_sqrt_sq (  .clock(clk),  .data(idin),  .result(dout)  ); always @ (posedge clk)   begin  $display ("idin= ", idin);   $display ("dout = ", dout);  end   endmodule    /****************ALTFP_SQRT CORE********************/   // megafunction wizard: %ALTFP_SQRT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altfp_sqrt  // ============================================================ // File Name: sel_sq.v // Megafunction Name(s): // altfp_sqrt // // Simulation Library Files(s): // lpm // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 10.1 Build 197 01/19/2011 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporation's design tools, logic functions  //and other software and tools, and its AMPP partner logic  //functions, and any output files from any of the foregoing  //(including device programming or simulation files), and any  //associated documentation or information are expressly subject  //to the terms and conditions of the Altera Program License  //Subscription Agreement, Altera MegaCore Function License  //Agreement, or other applicable license agreement, including,  //without limitation, that your use is for the sole purpose of  //programming logic devices manufactured by Altera and sold by  //Altera or its authorized distributors. Please refer to the  //applicable agreement for further details. module sel_sq (  clock,  data,  result)/* synthesis synthesis_clearbox = 1 */;  input clock;  input [31:0] data;  output [31:0] result; endmodule  /**********************testbench*************************/  module fp_sqrt (clk, idin, dout); input clk; input [31:0] idin; output [31:0] dout; wire [31:0] idin; wire [31:0] dout; sel_sq fp_sqrt_sq (  .clock(clk),  .data(idin),  .result(dout)  ); always @ (posedge clk)   begin  $display ("idin= ", idin);   $display ("dout = ", dout);  end   endmodule