Variable inside and outside a process

[Altera_Forum]

Hi, I'm having an problem that all I can think about to solve this is to use a variable inside an component and on every clock, increment it. 

With a loop it would also be possible, but I must increment by 8 and call a component inside a loop, what I believe isn't possible.  Here's an example:  LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE matrizes IS TYPE array_t IS ARRAY (0 TO 63, 0 to 63) OF STD_LOGIC_VECTOR(7 DOWNTO 0);  LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.matrizes.all;  ENTITY testt IS PORT (clk: in std_logic;  inpp: in array_t;  outpp: out array_t); END testt;  ARCHITECTURE behavior OF testt IS  VARIABLE a: INTEGER RANGE 0 to 64:=0;  COMPONENT test IS PORT (inp: in STD_LOGIC_VECTOR(8 DOWNTO 0)  outp: out STD_LOGIC_VECTOR(8 DOWNTO 0)); END COMPONENT  Process(clk) Begin if rising_edge(clk) then a:=a+8; end if; end process;  label_01: test PORT MAP (inpp(a, a), outpp(a,a));  END behavior;  I believe this code will not compile. It's just an example. I must every 50us for example, increment by 8 the array index:  label_01: test PORT MAP (inpp(a, a), outpp(a,a)); waits time  label_01: test PORT MAP (inpp(a+8, a+8), outpp(a+8,a+8));  Hope you can understand what I mean.  Thanks very much.

[Altera_Forum]

i don't sure i understand you.... 

but you can't directly affect variable inside the component. any dynamic communication with processes inside the component should be throw the components i/o. but you can copy a value from input port to internal variable and assign variable value to component output port.

[Altera_Forum]

There are at least two issues with your code: 

- You can't use a variable outside a process. Define "a" as a signal instead. - a will be actually implemented with a range of 0 to 127 (next higher binary range) and not comply with the index range of array_t. What is the intended next index after 56?

[Altera_Forum]

Thanks. 

That example is a way I thought maybe would do what I need.   I don't know how, but I need to do something like this:  for i in 1 to 64 (increment by 8: i.e. 0, 8, 16...) label_01: test PORT MAP (inpp(a, a), outpp(a, a)); end for;   OR I could do this: label_01: test PORT MAP (inpp(1, 1), outpp(1, 1)); label_02: test PORT MAP (inpp(8, 8), outpp(8, 8)); label_03: test PORT MAP (inpp(16, 16), outpp(16, 16)); But is too many times i must call the component, let's say 4096. So it's not possible do this way.  It's for image processing. I need to divide an image in 8x8 blocks. And put every individual block in a component If someone have some idea.  Thank you

[Altera_Forum]

FvM: 

It's wrong the range of array_t, so don't worry about that. But here is an example. Actually I will need to use much bigger values. I would be happy if only I could only increment one signal, or variable from time to time and use that variable on the array index of the component.

[Altera_Forum]

you're thinking too much like software. 

 components are NOT like functions in C. They are like chips on a circuit board. They exist all the time, and cannot be called as and when needed.  I think you may benefit from reading up on how logic works and digital circuit design.

[Altera_Forum]

I generally agree with Tricky, that you need to understand better the difference between hardware description language and software programming language. 

 Nevertheless, your original code can compile when implementing a as a signal. Of course, this doesn't necessarily imply, that it does something reasonable. I don't know the internal operation of the component "test". Your remark about "divide an image in 8x8 blocks" suggests, that you intend to use inpp(a, a) as a kind of pointer to subarray. But it isn't, it's just a single array element. If you mean a range, you have to write a range, e.g. inpp(a to a+7, a to a+7).  The correct method to create multiple instances of a component would be a generate statement rather than a loop. But as you already mentioned, it would involve a large resource requirement. The principle alternative is to perform the operation sequentially with a single component instance, which is basically described in your above code.  But there's a serious problem. The way you write the code, the array itself isn't but a huge amount of FPGA registers (or unregistered signal wires, depends on). Multiplexing this signals to single component involves even more FPGA resources and most likely won't work with practical array sizes.   I suggest, that you start with reviewing some basic image processing VHDL projects and try to understand, how they manage the data path. In most cases, they'll rely on FPGA internal RAM blocks or, in case of larger image arrays, external RAM. Then multiplexing becomes a resonable method. I'm sure, you'll also find text books dedicated to FPGA image processing.