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LVPECL with VCC of 3.3V on a Cyclone3

Altera_Forum
Honored Contributor II
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Hi, 

 

Is it possible to use LVPECL signals on a bank that has VCCIO = +3.3V? I am using a Cyclone3 part. 

 

Thanks
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Altera_Forum
Honored Contributor II
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The quick answer: No. 

 

The long answer: 

 

The Cyclone 3 handbook says LVPECL requires VCCIO of 2.5 V, and is only available on Clock Inputs of Cyclone 3 devices (Table 6-4 on page 6-13 of the handbook) 

 

That being said, quartus doesn't know what your real VCCIO is connected to, so you can say it's a 2.5V bank, but have it all hooked up to 3.3V, but the timing, and threshold levels wouldn't be guaranteed in this state, so it would be use at your own risk. However, if you state one item as 2.5V in the bank, (For the LVPECL), you would have to declare all IO's in that bank as 2.5V IO's, so you risk invalidating more than just the LVPECL thresholds and timing, but all the other IO's that are in that bank. 

 

If you need LVPECL outputs, you need to have an external LVPECL driver anyway. Since the Cyclone 3 doesn't support LVPECL drivers. 

 

Pete
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Altera_Forum
Honored Contributor II
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What dod you mean, LVPECL in- or output? 

LVPECL output can be emulated by respective resistive dividers, LVPECL as input can be interfaced with a LVDS receiver and level shifting resistors. But no differential I/O standard is specified to work with VCCIO of 3.3 V.
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Altera_Forum
Honored Contributor II
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I need LVPECL inputs. My only available banks have VCCIO of 1.8V and 3.3V. I am using a LMH7322 as a driver which provides PECL and LVDS outputs. Is there a way to level shift a LVPECL or LVDS signal to SSTL_18 so it can be used on the 1.8V bank?

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Altera_Forum
Honored Contributor II
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The problem is, that Cyclone III doesn't provide a differential input standard for VCCIO of 1.8V. You are able to divide down a single ended PECL output to met the SSTL-18 reference voltage, but the signal swing is below the specification, and I fear, the level will be also affected by temperatur variations. Without a true differential input, it's difficult to achieve reliable operation. 

 

Setting the comparators VCCO to minimal speicified 2.7V may bring you nearer to an acceptable solution. Personally, I would prefer external LVDS receivers.
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Altera_Forum
Honored Contributor II
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Which LVDS receiver do you prefer?

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Altera_Forum
Honored Contributor II
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Single gate devices like FIN1002.

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