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Hi :):),
My problem is when i try to recompile the project given by Stratix IV "board_update_portal" with a just change in PLL ( increase the frequency). I constate that the changement not taken it consideration, As i mentionned in http://www.alteraforum.com/forum/showthread.php?p=126717&posted=1#post126717. My question Now this problem dues to the License or NO? I note that i use a evaluation quartus 9.1. ThanksLink Copied
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If the design is using some opencore IP for which you don't have the license, it will create a time limited FPGA image. If your project is called myfpga, the resulting programming file will be called myfpga_time_limited.sof instead of just myfpga.sof.
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--- Quote Start --- If the design is using some opencore IP for which you don't have the license, it will create a time limited FPGA image. If your project is called myfpga, the resulting programming file will be called myfpga_time_limited.sof instead of just myfpga.sof. --- Quote End --- Thanks for you reply Daixiwen In my SOPC there are some IP core as CPU, PLL, ...etc. As i said: i use a evaluation version. On the resulting program i don't obtained _time_limited.sof.:(
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does the modified date on the resulting .sof file change, and does it reflect the actual compilation time?
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