how to declare dynamic port size depending on generic

Altera_Forum · ‎08-18-2011

Hi, Can anyone tell me how to declare a port with its size determine by a generic in VHDL?

For example:

ENTITY tone_det IS

generic(FRAME_SIZE: integer := 63;

.....);

PORT(

OUTPUT : std_logic_vector (5 downto 0);

......);

END tone_det;

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Here, the OUTPUT has a fixed size of 5 because 2^6-1=63. 63 is the frame size...but how to declare this dynamically? so everytime I change my generic (in a higher level design file), this OUTPUT size will be changed accordingly? For example, if generic is defined as 127, then the bus width should be 6

Thanks

Altera_Forum · ‎08-18-2011

Instead of defining FRAME_SIZE, define FRAME_WIDTH, then later inside your architecture define

constant FRAME_SIZE : integer := 2**FRAME_WIDTH-1;

Or, have two generics, FRAME_SIZE and FRAME_WIDTH, and where ever you instantiate the component have code in that architecture that defines

library ieee;

use ieee.math_real; -- ceil and log2

....

constant FRAME_SIZE : integer := 64;

constant FRAME_WIDTH : integer := integer(ceil(log2(real(FRAME_SIZE))));

....

u1: tone_det

generic map (

FRAME_SIZE => FRAME_SIZE,

FRAME_WIDTH => FRAME_WIDTH

);

port map (

...

Cheers,

Dave