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TSE TX SGDMA problem

Altera_Forum
Honored Contributor II
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Hi 

 

I had triple speed ethernet working in a system. I then added a PIO to the SOPC system, reasigned addresses and IRQs, regenerated and recompiled in Quartus. The ethernet is no longer working and when the system starts up I get this error: 

Error opening TX SGDMA init error -22 on netThe TX SGDMA is still in the system as before the only differnce is its base address. 

What can have caused this error? Anyone know how to fix it, or how to debug it?
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Altera_Forum
Honored Contributor II
322 Views

Do a screenshot of sopc system

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Altera_Forum
Honored Contributor II
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I manually changed the address of the TX SGDMA in SOPC to the address it had before when it was working and now it is working again.

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Altera_Forum
Honored Contributor II
322 Views

 

--- Quote Start ---  

i am facing also the problem 

--- Quote End ---  

 

 

Thats bad.
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Altera_Forum
Honored Contributor II
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It is certainly a software trouble. 

Have you rebuilt your system in order to use the new hardware addresses?
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Altera_Forum
Honored Contributor II
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The BSP was regenerated and the software recompiled but it did not work. To get it back to a working state I had to manually set the base address for the SGDMA back to what it was before I added the PIO and auto assigned the base addresses.

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Altera_Forum
Honored Contributor II
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You could add a printf call in your main file to print out the base address of the SGDMA as defined in system.h, to check that it is the same than in your Sopc project, because it looks like there in a mismatch there. 

Are you sure you generated the bsp with the correct .sopcinfo file, and that the image in the FPGA is the right one?
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Altera_Forum
Honored Contributor II
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Thank you for the tip. Adding a printf sounds like a good way to verify if there is any mismatch. At the moment my system is working, but I will keep this in mind in case I get this error or a similar error in the future. 

 

I think I must have generated the BSP correctly because the newly added PIO was working as it should. If the image on the FPGA was a wrong one I would have expected to get system id and time stamp mismatches which I did not get.
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