FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

constraint in a custom sopc component

Altera_Forum
Honored Contributor II
870 Views

Hi, i did a macro that enhance the contrast of an image. I have implemented as a sopc custom component. 

It has a pll inside that doubles the frequency for some elaboration and then i return to the normal frequency before output the results. 

 

I have 3 parallel channel for R G and B elaboration. 

 

If i use signal tap for watching the red channel, i see that the red data flows stable to the output instead of the green and blue data that give me some wrong results. 

 

I think signal tap is adding some constraint to the red channel and this helped. 

 

How i can constraint better my macro? 

In input i have the SOPC system clock. 

Is the internal clock related with the SOPC system clock? I think yes so i don't understand why i have these timing problems. 

 

Thank you
0 Kudos
0 Replies
Reply