- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello to everyone! I made a system with SOPC using a DDR2 with ALTMEMPHY IP and everything worked fine on SOPC.
However now i am trying to migrate my system from SOPC to QSys.. and it has been a nightmare to make it work... Has anyone made DDR2 w/ ALTMEMPHY on QSys work already? I have no compilation problems but it just doesnt work... I have some critical warnings saying it couldnt find pins of type addrcmd (?) matching my pin name...Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
A simple system with an ONCHIP-MEMORY works fine but if i add the DDR2 i can't even run NIOS from ONCHIP anymore.. it says it didnt find the SYSID, if i check the box to ignore the verification i get a processor not found / cannot stop the processor error..
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I upgraded to Q11 SP1 but the problem persists
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I had a similar issue with a DDR2 controller with Uniphy with it not finding my half rate clock. I had been changing a bunch of different setting so I'm not sure exactly when it happened. I ended up creating a new Qsys project from scratch and it cleared the issue. Not sure that's a big help but it's the only thing that got me going again.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Well i made one from scratch also but the problem persists. Seems like this IP isn't ready for QSys yet.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ok it's a QSys bug. You need to fix the Qsys generated topfile and insert output [0:0] wire in odt, cse and ckn signals
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page