Hi
I have an Aria II EP2AGX45 design with 2 PLLs which need to be driven from a single clock input. This clock is 2.5V LV-PECL, and one of the PLLs needs to be in a 1.8V bank.
This means, as far as I can see, that one PLL can be connected directly to the clock pins in the 2.5V bank, while the other 1.8V PLL (used in a Megawizard DDR2 memory controller) will need to be driven via a global clock network from a 2.5V bank clock pin.
1) The Aria II clock network chapter says: "The input clock to the PLL has to come from dedicated clock input pins or PLL-fed GCLKs/RCLKs only". What about GCLKs fed by dedicated clock input pins?
2) Is it possible to have the same clock pin directly drive a PLL, and also drive a global clock net? Will this compromise clock performance or integrity in any way?
3) Is there any downside to driving the PLL in a DDR2 memory controller from a pin-fed GCLK rather than a dedicated clock pin?
Thanks,
Chris
