Is arria II PLL good enough for DDR2 interface?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Is arria II PLL good enough for DDR2 interface?

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The Arria II GX PLL has 300 ps cycle to cycle jitter, max. All the DDR2 components I've looked at have a 250ps cycle to cycle jitter max spec.

I believe the PLL is providing the clock to the memory chip, so I'm wondering how the memory controller output clock is meeting the timing spec at the memory chip.

Has anyone looked at this problem?

Thanks,

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