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Hi,
I designed a FIR filter using verilog in Quartus and tested it in Modelsim. I designed the same filter in Matlab. My problem is initially I used 4-bit data as input and the results in Matlab and Modelsim matched. Then I tried with 16-bit data as inputs, but my Modelsim result is weird. When I plot the result of Modelsim using Matlab, and compare it with the Plot of results from Matlab, they both don't match. Could some one suggest me where my problem is. My verilog result has 36 bits to avoid overflow,but still the answers don't match.Link Copied
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