Verilog code errors???

Altera_Forum · ‎09-13-2011

Hi,

I have this piece of code which when compiled with Quartus II web free resulting in errors (follow comment //). Please advise how to fix them. Thanks.

1) assign Sclk = SCLKout;

assign CS_1 = (posedge Clk26mhz) ? CS1reg :

; // Error (10170): Verilog HDL syntax error at spi_intf.v(55) near text "posedge"; expecting an operand

assign CS_2 = (posedge Clk26mhz) ? CS2reg :

; //Error (10170): Verilog HDL syntax error at spi_intf.v(55) near text "posedge"; expecting an operand

Declaration: Sclk, Clk26mhz, CS_1, CS_2 as output type; SCLKout, CS1reg, CS2reg as reg type

2) assign# 500 rstb = 1'b0; 1'b1;

// Error (10170): Verilog HDL syntax error at tb_pcm.v(35) near text "1"; expecting "endmodule"

Declaration: rstb as wire

Note: the equivalent VHDL code (no error) is: rstb <= '0', '1' after 500ns;

Altera_Forum · ‎09-13-2011

First problem, you are trying to uses assign statements for registers.

Better to uses:

CS_1 and CS_2 would have to be defined as registers.

always @(posedge Clk26mhz)

begin

CS_1 <= CS1reg;

CS_2 <= CS2reg;

end

I'm assuming on your# 2, you are trying to do a test bench reset strobe where rstb = 0 for 500 ticks then 1.

This should be done in an initial block. and rstb defined as a register.

initial

begin

rstb = 1'b0;

# 500

rstb = 1'b1;

end

Altera_Forum · ‎09-13-2011

assign# 500 rstb = 1'b0; 1'b1;

Two comments:

- As shown, it's no legal Verilog syntax

- Verilog (as well as VHDL) delay statements are simply ignored in synthesis

Altera_Forum · ‎09-13-2011

I have another error:

if (Data_Lmt == 0)

begin

CS1reg <= 1'b1;

CS2reg <= 1'b1;

Databus <= SPIdata_reg; // Error (10137): Verilog HDL Procedural Assignment error at spi_intf.v(161): object "Databus" on left-hand side of assignment must have a variable data type

BUSY <= 1'b0;

Comm_RW_state <= SPI_RW_Statmachine_Read_repeat;

end

Declaration: databus is inout type of 8bits, SPIdata_reg is type reg of 8bits

Please advise. Thanks.

Altera_Forum · ‎09-15-2011

Nails is right, you cannot assign an inout type in an process, if did, how to handle the "in" part of the signal?