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what causes Verilog error?

Altera_Forum
Honored Contributor II
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I have another error when compiled with Quartus II: 

 

if (Data_Lmt == 0) 

begin 

CS1reg <= 1'b1; 

CS2reg <= 1'b1; 

Databus <= SPIdata_reg; // Error (10137): Verilog HDL Procedural Assignment error at spi_intf.v(161): object "Databus" on left-hand side of assignment must have a variable data type 

 

BUSY <= 1'b0; 

Comm_RW_state <= SPI_RW_Statmachine_Read_repeat; 

end 

 

Declaration: databus is inout type of 8bits, SPIdata_reg is type reg of 8bits 

 

Please advise. Thanks.
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Altera_Forum
Honored Contributor II
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Use (outside of any always blocks): 

assign Databus = SPIdata_reg; 

 

If it really needs to be a bidirectional inout signal type, you should have some sort of output enable signal and declare it as: 

 

assign Databus = output_enable? SPIdata_reg: 8'bz; 

 

if not, declare Databus as an output and use the simpler first assignment statement.
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Altera_Forum
Honored Contributor II
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Databus has to be inout type. The statement Databus <= SPIdata_reg; must be within that if loop and the if is within the always block... 

 

In this case, how could I fix this error? Thanks.
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Altera_Forum
Honored Contributor II
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I suggest you read up on some verilog tutorials instead of trying to 'wing it'. Verilog expressions do not execute like C or any other microprocessor programming language. But here's a more explicit explanation to get you pointed in the right direction. 

 

The "<=" operator feeds the right side expression (either the input port signal(s) or the Q output(s) of a register) to the D input(s) of the register on the left side. On the next clock cycle, the register on the left side will have latched the data and its output will reflect that and is ready to be used. Therefore, to use the "<=" operator, you must have a register type on the left side. 

 

Since Databus is declared as an inout port signal, rather than a register, you can't do it. There is no D input. Ports have no storage capability. If the port is not used internally by another parent module, then it will ultimately map directly to physical pin(s) on the device of the same name specificed in the quartus pin planner. 

 

You can continuously assign the port signal to the output of a reg type such as SPIdata_reg with the "assign" statement as I suggested earlier. 

 

As assign statements are continuous assignments, they do not belong inside an always block. 

 

To be explicit, the statement 

assign Databus = output_enable? SPIdata_reg: 8'bz; 

 

will assign the Databus port (pins) to SPIdata_reg (Databus[0] = SPIdata_reg[0], Databus[1] = SPIdata_reg[1], etc.) if output_enable is true, otherwise all Databus's signals will be tri-stated (the 8'bz part). That's the standard way of coding an inout port. 

 

Or in other words, SPIdata_reg's Q outputs will drive Databus's ports when output_enable is true. When output_enable is false, Databus's ports will be tri-stated to allow external signals to drive it's value. Presumably, some other portion of Verilog code would be reading Databus's value, and doing something useful with it at an appropriate time, such as storing it into a register, passing it back to the avalon readdata signal, etc. 

 

As a side note, what doesn't made sense to me is that you have a 8 bit wide bi-directional Databus for a SPI device. SPI devices communicate with one signal for output and one signal for input -- MISO and MOSI, so you've got more problems to address. 

 

Google Verilog tutorial. That's how I learned.
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