Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Hamming window

Altera_Forum
Honored Contributor II
1,601 Views

Can you please give me suggestion how do I design hamming window with verilog hdl on  

DE2 board ???
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
285 Views

In terms of Verilog, what you need to implement is a Nth order FIR filter. 

 

The filter's coefficients will be the Hamming window's coefficient.
0 Kudos
Altera_Forum
Honored Contributor II
285 Views

I am trying to design front end of speech recognition system on FPGA. 

I appreciate if you could provide me with useful resources which help me design a hamming window.
0 Kudos
Altera_Forum
Honored Contributor II
285 Views

Altera provides some filter IP. altera.com/support/examples/verilog/ver-fir-coefficient.html  

 

If you don't have access to the IP then you can build a FIR filter from scratch or get some examples online. Then generate the Hamming Window coefficients. (matlab will do this for you). 

 

Altera has some examples: altera.com/support/examples/exm-list.jsp?cat=dsp_filters_transforms&GSA_pos=4&WT.oss_r=1&WT.oss=FIR%20filter%20example
0 Kudos
Altera_Forum
Honored Contributor II
285 Views

rbugalho & winfrees, 

 

you suggestions were very useful. 

 

Thank you very much.:)
0 Kudos
Reply