Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Reprogram Max II CPLD?

Altera_Forum
Honored Contributor II
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During development, test, and debug, etc...can I reprogram the Max II CPLD many times via JTAG? if yes, do I need to do anything to erase the old program first before the new program could be programmed? what "file extension" do I choose for programming when select "Programmer" from the Quartus II?

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Altera_Forum
Honored Contributor II
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The device handbook specifies (only) 100 minimum erase and program cycles, so many times is relative. Typically, you can expect more, I never experienced an exhausted MAX II configuration flash. User flash endurance could be more problematic depending on the application. Sucessor MAX V has raised the user flash specification to 1000 cycles. 

 

*.pof files should be selected for programming, erase will be done automatically without performing it separately.
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Altera_Forum
Honored Contributor II
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if I program the Verilog/VHDL code into a Max II device, which CFM or UFM section do I program the code to? and I'm expecting to erase or reprogram the code repeatedly during the Test/Debug phase.

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