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Firstly, thank you in advance for any help you may be able to offer me. My question is as follows:
I am targeting the High Performance DDR2 controller for the Cyclone IV E (EP4CE40F23C8) device. I'm using the auto-generated "example_top" design file to functionally test the hardware. I have not been able to pass the DDR2 calibration/initialisation stage and reads/writes are failing. During the synthesis stage of compilation, I have noticed that some of the megafunctions within the DDR2 controller (ALTMEMPHY, DLL, DDIO) are being instantiated with the intended_device paramter set to "Cyclone III". Meanwhile some (example_top, example_driver, the top level controller vhd file) are being instantiated with the intended_device parameter correctly set to "Cyclone IV E". Is this normal behaviour and if not, could it explain why the DDR2 controller is not working? I have regenerated the megafunction several times and searched for and removed any references to CYCLONE III in my settings file. The device is consistently set to Cyclone IV E in the DDR2 megafunction and elsewhere in my project settings. I have been unable to find an explanation for this in any errata or documentation. Details: Device: EP4CE40F23C8 Quartus II version 11 sp1, Windows XP full edition Any help is truly appreciated!Link Copied
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