Programing 5M80ZE64C5N MAX V CPLD

[Altera_Forum]

Hi, 

 I'm getting this error when I try to program the 5M80ZE64C5N MAX V CPLD:  Info: Started Programmer operation at ... Info: Device 1 contains JTAG ID code 0x020A50DD Error: Can't recognize silicon ID for device 1 Error: Operation failed Info: Ended Programmer operation at ...  In the "Device" I choose 5M80ZE64C5 since the ...C5N isn't an option. Nevertheless, in the "MAX V Device Handbook", "Chapter 6: JTAG and In-System Programmability in MAX V Devices" w w w.altera.com/literature/hb/max-v/mv51006.pdf, in Table 6–3. 32-Bit IDCODE for MAX V Devices, it is stated that the HEX IDCODE for the 5M80Z devices is 0x020A50DD.  I have no clue of what I can do to solve this.  Kind regards Pedro Ferreira

[Altera_Forum]

What version of Quartus (or the programmer) are you using? 

 The error messages indicate that the programmer reads the JTAG ID correctly, but when it tries to match that device to its hard-coded list of supported devices, it does not find it. You likely need to use the most recent version of Quartus to get the updated list of device IDs.  Cheers, Dave

[Altera_Forum]

Hi, 

 I'm using Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition. I suppose this is the latest version.  My programmer is Altera USB-Blaster, because I already have it. Didn't read anything about any incompatibility with the new MAX V CPLD's, but also haven't read about its compatibility...  Kind regards Pedro Ferreira

[Altera_Forum]

I never met "Can't recognize silicon ID" except with indirect JTAG programming of configuration devices. You are trying to write a *.pof file to the MAX V device?

[Altera_Forum]

--- Quote Start ---   I'm using Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition. I suppose this is the latest version.   --- Quote End ---  That sounds recent enough.    --- Quote Start ---   My programmer is Altera USB-Blaster, because I already have it. Didn't read anything about any incompatibility with the new MAX V CPLD's, but also haven't read about its compatibility...   --- Quote End ---  The USB-Blaster you have must be working fine, since it reads the silicon ID.  How did you create the file you are trying to download?  I just tried using the Quartus 9.1 programmer to open a .pof download file for a Cyclone IV (which would be unsupported in that version), and it gives the error that EP4CE22F17C7 is not supported (this is the BeMicro-SDK FPGA).   If Quartus 11.0 did not support your device, then I would expect to see a similar error.  Does the JTAG programmer 'auto detect' the correct part number?  Altera has recently screwed-up their part IDs, with some devices now having the same silicon IDs. For example Quartus 9.1 auto-detected the Cyclone IV device as a EP3C25.  Perhaps your programming file was created for a difference device ID. Check that your design project has the correct part number.  Cheers, Dave

[Altera_Forum]

Hi, 

 Yes, the programing file is *.pof. I made an simple moore state machine with a Verilog template, just compile it without errors and open the programmer, it show me the *.pof file. It must be *.sof? In the interactive tutorial it is programmed an *.sof. What is the diference?  In the "JTAG Chain Debugger" I get this log: Info: JTAG chain connection is good. Detected 1 device(s) Info: Device 1: 5M(160Z|240Z|40Z|80Z)/.. (USERCODE: 0x00000000)  The same ID is shared with those 4 devices, as I said mine is 5M80ZE64C5N.  In the"Device support release notes (PDF)" of this version, it is written that is as compatibility with all of the MAX V devices.  Kind regards Pedro Ferreira

[Altera_Forum]

Could you please confirm that in Quartus II, Assignments->Device has the 5M80ZE64C5N selected. 

 Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Like I said, in the "Device" I choose 5M80ZE64C5 since the ...C5N isn't an option.  I don't know the differences between the two, but I suppose it shouldn't be a problem. Or it should?  Kind regards Pedro Ferreira

[Altera_Forum]

--- Quote Start ---   Like I said, in the "Device" I choose 5M80ZE64C5 since the ...C5N isn't an option.   --- Quote End ---    Ok, I just wanted to confirm that was the 'device' setting.    --- Quote Start ---   I don't know the differences between the two, but I suppose it shouldn't be a problem. Or it should?   --- Quote End ---    The N just means RoHS (no lead).  Do you have other boards with different devices that work? (Just wondering if this is a software setup issue ....)  Cheers, Dave

[Altera_Forum]

Is this an Altera kit? 

 Find a *.pof in the kit software download, and see if it works.  ... just throwing ideas out there ...  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  It must be *.sof? In the interactive tutorial it is programmed an *.sof. What is the diference?  --- Quote End ---   *.pof is correct for MAX devices. *.sof is for (volatile) programming of FPGA. But except for having other programmer options, operation is almost the same.

[Altera_Forum]

No this is a self made pcb, for a Software defined GPS. 

 But I'm going to try that.  Kind regards Pedro Ferreira

[Altera_Forum]

I opened an oscillator example, compiled it and run the programmer, and now I get this error: 

Info: Started Programmer operation at Thu Sep 15 22:53:13 2011 Error: Can't configure device. Expected JTAG ID code 0x020A60DD for device 1, but found JTAG ID code 0x020A50DD. Error: Unexpected error in JTAG server -- error code 44 Error: Operation failed Info: Ended Programmer operation at Thu Sep 15 22:53:13 2011  So I verified the device and it is assigned to 5M570ZF256C5. It corresponds the ID from the Handbook, but unfortunately it isn't my device.  Kind regards Pedro Ferreira

[Altera_Forum]

At least I know that this version os Quartus has the MAX V compatibility, since it knows the ID for the 5M570ZF256C5 CPLD.

[Altera_Forum]

Hi, 

 Any ideas? I still can't program my Max V, and I'm out of ideas.  In the design layout I didn't supply voltage to the bank 2 leaving their pins in air. Should I supplied it? I have 3.3V on VCCINT and 1.8V on VCCIO1, and with each vcc pin I put a 100nF decoupling cap. The development board has 2 x 100nF and a 10uF in parallel, per VCC Pin.  Does anyone has been successful programing 5M80ZE64C5N CPLD? Or any other MAX V CPLD besides the development board that has an incorporated USB-Blaster? If so, does anyone has a *.pof program file designed for 5M80ZE64C5N CPLD for me to program? So I can put aside the cause from the software and focus on the hardware.  Kind regards Pedro Ferreira

[Altera_Forum]

--- Quote Start ---   In the design layout I didn't supply voltage to the bank 2 leaving their pins in air. Should I supplied it?   --- Quote End ---    Did you read the handbook?  http://www.altera.com/literature/hb/max-v/max5_handbook.pdf  Try reading section 4. Hint ...  "All VCCINT and VCCIO power supplies of all banks must be powered on before entering user mode"  Cheers, Dave

[Altera_Forum]

Hi, 

 That was the problem!!! I managed to solder two wires for supply and put the decoupling caps, and it worked!:lol:  When I was designing the schematic I thought that if I wasn't using the bank2 I didn't need to give it supply, and with this fault I spend a week banging my head on this..  Thanks a lot for the help and quick responses, Kind regards Pedro Ferreira

[Altera_Forum]

I'm glad to hear its now working. 

 It always pays to read the user manual doesn't it :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Yes, it was a big relief for me. Although, sometimes the programming fails at half the percentage, but if I put my finger on the IC it resolves =D (not in the manual =P)  Yes, I resorted to the manual at different stages of the project, but I didn't read it all :  Once again big thank you Kind regards Pedro Ferreira

[Altera_Forum]

--- Quote Start ---   Although, sometimes the programming fails at half the percentage, but if I put my finger on the IC it resolves =D (not in the manual =P)   --- Quote End ---  Finger on the IC, or on the pins (sometimes a finger causes both to happen)?  If its related to your fingers touching the pins, then you are likely acting as a 'decoupling capacitor' and you are either affecting a JTAG signal, or a power-rail.  Decoupling capacitors should be placed on every power pin. Ideally the capacitors go at the end of every pin, or are placed at vias directly underneath the power pins (or BGA pads).  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 The problem is that the actual PCB wasn't designed to have the supply for the Bank2, so I had to do some magic in soldering to put a decoupling cap in the two supply pins of the IC (EQFP) and above the cap I solder the the wire to supply the voltage. Its not how it should be but as this is a prototype of the final board, I have to manage something.  The finger is on the pins, because I put the decoupling capacitor and the wire for supply, and isolated with hot glue.  After the testings I'm going to make a final board with this problem solved.  Kind regards Pedro Ferreira