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Verilog code to block diagram

Altera_Forum
Honored Contributor II
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Hello Folks, 

 

I am very new to FPGAs/CPLDs so sorry if I'm asking something trivial but I am digging around the net for days now finding the answer to my problem. Unfortunately I couldn't find any tutorials or examples on how to make a new schematic block from a verilog code. 

 

For example, I have a short code: 

 

`timescale 1 ps / 1 ps module SORD_PWM (Clock_In, Enabled, PulseS, PulseR); input Enabled, Clock_In; output PulseS, PulseR; reg PulseS, PulseR; reg ThresS = 200; reg ThresO = 12; reg ThresR = 200; wire Enabled; reg Saw = 0; reg Reset; always @ (posedge Clock_In) if(Reset) Saw = 0; else begin PulseS = Saw <= ThresS; PulseR = (Saw - ThresO) <= ThresR; Saw = Saw + 1; end endmodule 

 

So how can I put this code in a block diagram that will represent a custom symbol, has wire connections, etc? It would be rather visual for educational purposes. 

 

Many thanks 

 

Best Regards 

Tony
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Altera_Forum
Honored Contributor II
928 Views

  • Keep opened this verilog file in quartus and go to 

 

 

--- Quote Start ---  

file-->create/update-->create symbol files for current file 

--- Quote End ---  

 

  • Symbol file will be " <you current file name> . bsf".Then you can add with other blocks for connections. 

  • You will get lines named "Enabled, Clock_In" at input side and "PulseS, PulseR" output side of the block. 

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Altera_Forum
Honored Contributor II
928 Views

Great! It works! 

 

Many thanks 

 

Kind Regards 

Tony
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