VHDL state to entity

[Altera_Forum]

Hi, 

 I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement.  Please let me know how to do this.  Regards, freak

[Altera_Forum]

add an output port with your favorite name, then 

 curr_state_out <= curr_state;  This should keep your customer happy.

[Altera_Forum]

Hi kaz, 

 This is throwing error. I had already tried this.  The error is copied below,  Error-[SEQSTMTASSIGNTYPE] Type mismatch ../dut/state_machine.vhd, 33 SYNTH    outp_state <= cur_state;  ^  The assignment statement target data type does not match the source data   type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and   is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is   'STATE' and is declared by 'ARCHITECTURE SYNTH'.  "../dut/state_machine.vhd": errors: 1; warnings: 0.    This occurs because our state variable is user defined and ouptut port is std_logic_vector. The state definition is copied below;  type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7); signal cur_state, nxt_state : state;   Any idea to override this or any convesion function.  Regards, freak

[Altera_Forum]

Hi, 

 Good point. There might be some of those special tool statements to do that(Only FvM knows those secrets) but if it is me I will regenerate a bit of logic:  case cur_state is when idle => out_p <= "000"; when s1 => out_p <= "001"; ...etc.  i.e. you convert it to numerical value onto std_logic_vector.  Regards

[Altera_Forum]

CurrentStateOut : out std_logic_vector( ceil(log2( number of states )) - 1 downto 0) ; --- CurrentStateOut <= std_logic_vector( to_unsigned( state'pos(curr_state) , ceil(log2( number of states )) ) ;  

You have to replace the ceil(log2( number of states )) in the port declaration by a fixed number as the size of 'state' is only defined until later in the architecture section. If the output is only required for simulation or documentation purposes you could define the output port as a natural:  CurrentStateOut : out natural ; ... CurrentStateOut <= state'pos( curr_state) ;  simple, and you don't have to modify the code in case the 'state' definition changes during the design. The only drawback is that the natural is represented as a 31-bit vector, so you may want to restrict the range of the natural.

[Altera_Forum]

Thanks JosyB, 

 In layman terms like myself I believe you mean:  port declaration: CurrentStateOut : out std_logic_vector(2 downto 0);   then in assignment section:  CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state),3));  Hopefully that will do if tool support doesn't get in the way.

[Altera_Forum]

Sorry if I sounded like a preacher:) 

I verified the solution in QII 9.1SP2 before committing the post. Attributes are well specified in the VHDL LRM so I don't think that ModelSim will choke on it. (if it does tell me)

[Altera_Forum]

Using the state'pos attribute is in fact the most reasonable way.  

 Alternatively, you can also use the state type in the entity interface, you get a bit vector according to the state machine encoding, one-state-hot state by default. The type has to be defined in a package.  P.S.: In terms of logic effort, the pos attribute does the same as decoding the states to numbers, as kaz suggested. The internal representation of the state variable will be still one state hot.

[Altera_Forum]

Hi FvM, 

 Can you please provide an example.  One more thing, Is natural data type synthesizable. ?  Regards, freak

[Altera_Forum]

Hi vlsi_freak, 

 But Josyb answered you, I simplified his post and FvM endorsed it.  Regards

[Altera_Forum]

The code below looks to be working, 

CurrentStateOut : out natural ; CurrentStateOut <= state'pos( curr_state) ;  The below code is giving out error,  CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state) ,3));   Is data dype 'natural' can be synthesized.

[Altera_Forum]

obviously the attribute is recognised but what does the error read?

[Altera_Forum]

Like I said I always verify before I post. My code: 

State : out std_logic_vector( 1 downto 0) ; StateN : out natural ; ... State <= std_logic_vector( to_unsigned( states_camerastatusLED'pos( smp ) , 2 ) ) ; StateN <= states_camerastatusLED'pos( smp ) ;  What error did you get? Did you include the IEEE numeric_std library?  The natural data type will synthesize to a 31bit-wide vector. You can see this in the 'Tools->RTL Viewer' window. You can constrain the range of the natural to 7 in your case, and you will end up with just 3 pins synthesized.  CurrentStateOut : out natural range 0 to 7 ;

[Altera_Forum]

--- Quote Start ---  Is natural data type synthesizable  --- Quote End ---   Yes, josyb implied this by mentioning the default size of 31 bits. Something like natural range 0 to 7 would be more appropriate for synthesis.   But you should consider, that a type with implicite bit definition has some disadvantages in pin assignment.

[Altera_Forum]

Hi, 

 Please see my code below (coded as per the current thread) and the error log;   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; entity statemachine is port ( clk : in std_logic; rst : in std_logic; proceed : in std_logic; data_out : out std_logic; outn_state : out natural range 0 to 7; outp_state : out std_logic_vector(2 downto 0) ); end entity; architecture SYNTH of statemachine is type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7); attribute syn_enum_encoding: string; attribute syn_enum_encoding of state : type is "000 001 010 011 100 101 110 111"; signal cur_state, nxt_state : state; begin outn_state <= std_logic_vector(to_unsigned(state'pos(cur_state),3)); outp_state <= state'pos(cur_state);    The error log is copied below; ************************************************************************ vhdlan state_machine.vhd  Synopsys 1076 VHDL Analyzer  Version D-2010.06-SP1-8 -- Aug 13, 2011  Copyright (c) 1991-2010 by Synopsys Inc.  ALL RIGHTS RESERVED  This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.  Parsing design file 'state_machine.vhd'  Error-[SEQSTMTASSIGNTYPE] Type mismatch state_machine.vhd, 31 SYNTH    outn_state <= std_logic_vector(to_unsigned(state'pos(cur_state),3));  ^  The assignment statement target data type does not match the source data  type. The target data type is 'Anonymous subtype of INTEGER' and is  declared by 'PACKAGE STD.STANDARD'. The source data type is  'STD_LOGIC_VECTOR' and is declared by 'PACKAGE IEEE.STD_LOGIC_1164'.  Error-[SEQSTMTASSIGNTYPE] Type mismatch state_machine.vhd, 32 SYNTH    outp_state <= state'pos(cur_state);  ^  The assignment statement target data type does not match the source data   type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and   is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is   'UNIVERSAL INTEGER' and is declared by 'PACKAGE STD.STANDARD'.  "state_machine.vhd": errors: 2; warnings: 0. ************************************************************************  Please guide me to clear the error.  Regards, freak

[Altera_Forum]

swap over n and p for the two outputs. You're trying to assign an integer to the std_logic_vector and slv to the integer.

[Altera_Forum]

also remove: 

use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; they are deprecated and (may) conflict with the numeric_std library

[Altera_Forum]

Thanks a lot Josyb. Its workig. 

 Regards, freak

[Altera_Forum]

What's your motivation for state machine user encoding? You can assume, that the default one state hot encoding is optimized for FPGA synthesis.

[Altera_Forum]

You mean, by default the tool uses one-hot encoding. 

 Regards, freak

[Altera_Forum]

--- Quote Start ---  You mean, by default the tool uses one-hot encoding.  Regards, Jaseel  --- Quote End ---    If you have more than 3 states, the default is one hot.