- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
how is the signed multiplication performed using an M_by_M carry save array multiplier ???
Link Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Are you asking about how this type of multiplier works at silicon level (its architecture) or are you asking how to multiply in fpga?
I personally don't know about various architectures of multiplier technology, I just multiply and get the output and leave that to the tool.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Are you asking about how this type of multiplier works at silicon level (its architecture) or are you asking how to multiply in fpga? I personally don't know about various architectures of multiplier technology, I just multiply and get the output and leave that to the tool. --- Quote End --- thanks for replying Kaz, i meant the architecture, i want to implement my own, i did the unsigned on but not familiar with the signed one(s)...
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We here work on fpga platforms and make use of ready-made blocks of rams/mults/possibly adders/PLL/serdes ..etc. The rest of functions are left to designers to implement in the logic fabric. So we have little choice of available sub-components.
I know Universities don't draw a clear line between fpga and asic as they prepare students for all areas. Thus the best place for your question is an ASIC forum, they are proud people and know a lot about silicon level design.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Some examples of multiplier architectures are discussed in the Quartus Advanced Synthesis Cookbook
http://www.altera.com/literature/manual/stx_cookbook.pdf Personally, I'm satisfied with the multiplier implementation of the Quartus integrated synthesis, particularly using FPGA hardware multipliers of recent FPGA families.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page