- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hey,
I am trying to generate horizantal sync pulse with FSM. I write the next verilog code:
module horizantal_sync_pluse (
clock, //system clock
reset, //system reset
sync_pulse //horizantal sync pulse
);
//State machine parameters
parameter Scan_Line=1'b0;
parameter Gen_Sync_Pulse=1'b1;
//----------------------------------
input clock;
input reset;
output sync_pulse;
reg sync_pulse;
reg state;
reg counter;
always@(posedge clock, negedge reset)
begin
if (reset==0)
begin
state<=Gen_Sync_Pulse;
sync_pulse<=1'b0;
end begin
case (state)
Gen_Sync_Pulse:
if (counter==11'h00BC) begin //188
counter<=counter+1'b1;
state<=Gen_Sync_Pulse;
sync_pulse<=1'b0;
end else
begin
state<=Scan_Line;
end
Scan_Line:
if (counter==11'h639) begin
sync_pulse<=1'b1;
counter<=counter+1'b1;
state<=Scan_Line;
end else
begin
state<=Gen_Sync_Pulse;
counter<=0;
end
default:
state<=Gen_Sync_Pulse;
endcase
end
end
endmodule
after compilation I get Warning: Latch counter[0] has unsafe behavior Warning: Ports D and ENA on the latch are fed by the same signal sync_pulse~5 This warning is on each bit of the counter. why is it? how can I avoid it? Thanks
Link Copied
7 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I haven't done verilog for years but I think you got simple error,
if reset == 0 begin ..... end else begin // you should put else here ....- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks. it happens to me sometimes, skip on this or that word. very diffecult to find asuch mistake by myself.
Thanks again- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Well you can just not declare the unwanted parameters and use their assigned values directly in your code to replace their names.
Parameter is for helping code readability/updating only. At compile time they are replaced by its value.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- I would like define parameter Scan_Line=1'b0; parameter Gen_Sync_Pulse=1'b1; How can I do it? --- Quote End --- Try localparam Scan_Line=1'b0; localparam Gen_Sync_Pulse=1'b1; Cheers, Dave
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Well Dave, I should add you to the list of My Gurus. So far only FvM and josyb managed to get there.
Regards- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hey Kaz,
--- Quote Start --- I should add you to the list of My Gurus. So far only FvM and josyb managed to get there. --- Quote End --- You are too kind. I just happened to see localparam used in some of the Altera Verilog :) Cheers, Dave
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page