SystemVerilog Extensions Error

Altera_Forum · ‎09-27-2011

Trying to declare a bidimensional array as input in a module.

I get the following error during synthesis

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Error (10773): Verilog HDL error at FFT04.v(3): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions

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module declaration is the following:

module test(A,Y);
input wire signed  A ;
Is this a basic HDL error or can be solved setting some Quartus feature?

Thanks in advance

Altera_Forum · ‎09-27-2011

Did you set Verilog input options to System Verilog?

Altera_Forum · ‎09-28-2011

No I didn't.

After doing it everything is fine.

Thanks for your answer.

This, however, means working with SystemVerilog. Hope not to loose too much in compatibility.

Altera_Forum · ‎09-28-2011

one thing you'll run in to is that Quartus won't make example instantiations of SystemVerilog modules with multi-dimensional ports

Altera_Forum · ‎09-28-2011

you can also set SystemVerilog mode per file instead of globally. in fact if you name the file .sv it may do this for you, if not i think there's a synthesis attribute or an assignment

Altera_Forum · ‎09-28-2011

For pancake,

can you tell me what is an "example instantiation" of a module?

Altera_Forum · ‎09-30-2011

sounds like you don't use the feature, so its a non-issue :)

if you open an HDL file and go to File > Create/Update > Create Verilog Instantiation

Quartus will create an example instantation for the source HDL. it won't work with System Verilog multi-dimensional ports