Yet Another Verilog Inconvenience

[Altera_Forum]

When trying to build a QSys module for my own building block I got the following error: 

  --- Quote Start ---  Error: Error: Error (10867): Verilog HDL or VHDL XML Interface error at sensor.vhd(60): port "SQ" has an unsupported type File: /qdesigns/bv5-develop/bb/sensor/sensor.vhd Line: 60   --- Quote End ---   This the offending line:  SQ : out std_logic_2D(15 downto 0, 9 downto 0) ;   The std_logic_2d is a VHDL data type created by Altera (in the lpm_pack.vhd library, adding this file to the filelist didn't help) to match the AHDL double indexed array, e.g. SQ[n..0][m..0]. As I moved from AHDL to VHDL I used this type a lot to interface with existing AHDL modules. Later on I kept (and keep) using this std_logic_2d tn my VHDL work as this is the only way to create true generic interfaces (at least before VHDL2008). Now Altera has decided to use Verilog internally and that is fine by me, but they should support their own (and subsequently my) legacy code? Or have they lost their pride? Somebody must have stumbled on this before me?

[Altera_Forum]

in my opinion, the std_logic_2d type was a fudge that was ****, that made it incompatible with any other code. 

 I dont quite understand why they didnt just do arrays like everything else - an array of std_logic_vectors.

[Altera_Forum]

Until VHDL2008 you couldn't create an array of unconstrained std_logic_vectors.  

In AHDl you could specify a port with a double index, e.g. SQ[m..0][n..0] and have m and n parametrised by the caller. With VHDL1993 the best match was : type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SQ : input -> SQ : in std_logic_2D(m downto 0, n downto 0); Didn't look too kludgey to me ... Using arrays of constrained std_logic_vectors requires the use of packages to declare the created type before it can be used in the port declaration, which is hardly a generic interface.  Wouldn't the SQ[m..0][n..0] in AHDL be correctly represented by wire SQ or does that only work for 'reg'?  Anyway in QSys there is that strict notion of Symbols and Words which makes it impossible to have a ST-Source feed multiple datasets ( e.g. a std_logic_2D signal and a std_logic_vector signal) out to the next ST-Sink. Unless you start using multiple conduits and connect those in QSys as well. So I packed everything into a kludgey aggregated std_logic_vector and declared the symbol width equal to the size of that vector.