VHDL array syntax

[Altera_Forum]

I'm just trying to test out writing out arrays in VHDL but I can't get it to work. The error I get is Error (10568): VHDL error at Testarray.vhd(16): can't write to interface object "a" of mode IN 

  Library ieee; USE ieee.std_logic_1164.all;  ENTITY arraytest is   PORT (  a : IN STD_LOGIC_VECTOR (3 downto 0);  z : OUT STD_LOGIC  );   END;  ARCHITECTURE assignment OF arraytest is BEGIN    a <= "1100";  z <= a(0) and a(1); END;  Thanks.

[Altera_Forum]

The problem is with line a <= "1100"  

You can't assign 'a' since this is an input port, so its assignment is supposed to come from an external signal. In other words, you must instantiate this entity in a upper level and drive the a input port.