Verilog bug, DE2-70 board

Altera_Forum · ‎10-01-2011

I've got a fairly simple bug and I don't have a clue how to work around it without getting silly.

I'm implementing a fairly simple FIR filter in Verilog and using the buttons and switches to do some basic testing. The problem is that it is somehow optimizing away my last delay stage, but only if I don't look directly at the stage.

Below I've got a bit of code. If the line

wire [15:0] bob = 2;//delay[2];

is replaced with

wire [15:0] bob = delay[2];

then the code works perfectly. Otherwise the delay 1 and delay 2 stages get combined.

To test: run code with standard qsf file. Set all switches to "0" other than sw0. Press key 3 a few times. HEX0 will count 0, 1, 3. It should count 0,1,2,3. If you change the code it _will_ count that way.

Clues?

Is quartus known to not handle arrays of buses correctly? Mixing blocking and non-blocking assignments? I realize this could somehow be my fault, but heck if I can see how.

Arg!

====

module lab4(

input [17:0]SW,

input [3:0] KEY,

output [7:0] HEX0,

output [7:0] HEX1,

output [7:0] HEX2,

output [7:0] HEX3,

output [7:0] HEX4,

output [7:0] HEX5,

output [7:0] HEX6,

output [7:0] HEX7

);

wire ver=4'd1;

parameter ORDER=2;

reg [15:0] delay [ORDER:1];

wire [15:0] coef [ORDER:0];

reg [31:0] sum;

wire [15:0] bob = 2;//delay[2];

assign coef[0] = 1;

assign coef[1] = 1;

assign coef[2] = 1;

//`include "coef.v"

bh one (KEY[0]?sum[3:0] :bob[3:0] ,HEX0);

bh two (KEY[0]?sum[7:4] :bob[7:4] ,HEX1);

bh three (KEY[0]?sum[11:8] :bob[11:8] ,HEX2);

bh four (KEY[0]?sum[15:12]:bob[15:12] ,HEX3);

bh five (sum[19:16],HEX4);

bh six (sum[23:20],HEX5);

bh seven (sum[27:24],HEX6);

bh eight (sum[31:28],HEX7);

integer i;

always@(negedge KEY[3])

begin

sum=SW[15:0]*coef[0];

sum=sum+delay[1]*coef[1];

delay[1]<=SW[15:0];

for(i=2;i<=ORDER;i=i+1)

begin

delay <= delay[i-1];

sum=sum+delay*coef[i];

end

endmodule

`define n0 7'b1000000

`define n1 7'b1111001

`define n2 7'b0100100

`define n3 7'b0110000

`define n4 7'b0011001

`define n5 7'b0010010

`define n6 7'b0000010

`define n7 7'b1111000

`define n8 7'b0000000

`define n9 7'b0010000

`define na 7'b0001000

`define nb 7'b0000011

`define nc 7'b1110000

`define nd 7'b0100001

`define ne 7'b0110000

`define nf 7'b0001110

module bh(bin, hex);

input [3:0] bin;

output [6:0] hex;

assign hex = (bin == 4'h0) ? `n0:

(bin == 4'h1) ? `n1:

(bin == 4'h2) ? `n2:

(bin == 4'h3) ? `n3:

(bin == 4'h4) ? `n4:

(bin == 4'h5) ? `n5:

(bin == 4'h6) ? `n6:

(bin == 4'h7) ? `n7:

(bin == 4'h8) ? `n8:

(bin == 4'h9) ? `n9:

(bin == 4'ha) ? `na:

(bin == 4'hb) ? `nb:

(bin == 4'hc) ? `nc:

(bin == 4'hd) ? `nd:

(bin == 4'he) ? `ne: `nf;

endmodule

Altera_Forum · ‎10-01-2011

You need to write a testbench and simulate your code so you can see what's going on.

I wrote this following your instructions and I can't get it to work in either case.

`timescale 1 us/1ns

module lab4_tb;

wire [17:0] SW = 18'h1;

reg [3:0] KEY;

wire [7:0] HEX0;

wire [7:0] HEX1;

wire [7:0] HEX2;

wire [7:0] HEX3;

wire [7:0] HEX4;

wire [7:0] HEX5;

wire [7:0] HEX6;

wire [7:0] HEX7;

lab4 uut (SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

integer i;

initial begin

KEY <= 4'h0;

for(i = 0; i < 100; i = i+1) begin

# 10; KEY[3] <= 1'b1;# 1 KEY[3] <= 1'b0;

end

endmodule

Altera_Forum · ‎10-01-2011

Thanks for all the effort! I suspect it won't simulate correctly because KEY[0] is a zero (buttons are active low on the board, so the default would be high). I'll give that a try in a bit when I get in the lab in a few minutes...

Thanks again,

Mark