Impossible to configure Cyclone III with JTAG

[Altera_Forum]

Hello, 

 I have a problem with Cyclone III EP3C25F324 device programming. I'am using a board with 1 cyclone III, a EPCS128 device and a PC28F128P30BF65E flash.  Flash Ram is not connected to the dedicated pins on FPGA. It's a mistake on my design. The MSEL pins are configurated for AP configuration (MSEL bits : 1011). The EPCS128 device is connected on the AS configuration.   When I connect the USB-Blaster, the JTAG chain is not accessible.  nSTATUs stuck at low.  nCONFIG at +2.5V nCE at 0V  Do you think nSTATUs doesn't leave the low level because of a wrong configuration (MSEL) or because of faults on power supply ?

[Altera_Forum]

The JTAG chain should always be accessible, even if the MSEL configuration is bad. You should check the power supplies, and the JTAG signals with a scope.

[Altera_Forum]

Thanks for your quick answer. 

All my power supplies are good. TCK Hight level is 2V instead of 2.5V). But some VREF pins are not connected.   Do I have to connect VREF to VCCIO or GND if I don't want to use it ?

[Altera_Forum]

No you don't have to connect the VREF pins to anything. 

How di dyou measure the TCK high level? Are the signals toggling when you attempt to access the component through JTAG? How are the JTAG pins connected and which pull ups/down did you use? Are you sure that the BGA balls are soldered correctly?

[Altera_Forum]

Hi, 

I've checked JTAG signals with a scope. TDI, TDO, TMS have a good 2.5V High level. But TCK have a 2.5V/100ns overshoot before a 1.5V high level. But toggle correctly. (see picture).  https://picasaweb.google.com/109130808728084231321/7Octobre201102?authuser=0&feat=directlink

[Altera_Forum]

I don't see any image. 1.5V seems rather low... could you show the schematics of your JTAG connection?

[Altera_Forum]

Hi, 

 I found the problem, thank you for all your answers.  My USB-Blaster is out of order just for TCK.  I'm programming now with my old Byte-Blaster ...