How to receive slow bit stream data using GXB

[Altera_Forum]

Hi,  

 Is there a way to use the GXB in Stratix IV to recover data/clock from a bit stream slower than 600Mbps? I know Xilinx transceivers can do this using oversampling.  Thanks, Hua

[Altera_Forum]

--- Quote Start ---   Is there a way to use the GXB in Stratix IV to recover data/clock from a bit stream slower than 600Mbps? I know Xilinx transceivers can do this using oversampling.   --- Quote End ---  Do you have a reference for the Xilinx statement?  The Altera documentation also states that you can use over-sampling to receive data ... though it may only apply to data. You need to be careful when reading marketing material :)  The CDR uses data transitions to generate a signal to lock the PLL to. I would be surprised if you could lock a CDR programmed to expect a data rate of 1Gbps with transitions only at 500Mbps or 250Mbps. However, if you keep the CDR in lock-to-reference mode, and both the transmitter and receiver use a common reference, then you could use the eyeQ feature to get the receiver in the center of the eye, and use logic at the output to check that each over-sampled sample has the same value, eg. pairs of oversampled-by-2 have the same value.  You'll have to perform some hardware tests to see if you can see what works and what does not.  Cheers, Dave

[Altera_Forum]

The Stratix IV transceiver CDR is specified with a maximum run length of 200 UI. It's also clear that non-8B/10B-coded streams and DC coupling are supported. In so far, there should be a wide range of possible protocol implementations, including the said oversampling of lower bit rates than 600 MBPS. 

 The coding properties (run length, balancing) will still matter for the achievable performance.

[Altera_Forum]

Hi Dave, 

 Thank you for your reply. You are right, Xilinx only do data in this scenario. We have a product using this feature from Xilinx right now, I don't know the details but Xilinx transceiver picks the sample point close to the middle automatically based on statistics.   Do you mind point me to the Altera documentation you mentioned about using over-sampling to receive data? Is the phase picking process automated on Altera side?  Thanks, Hua

[Altera_Forum]

Hi FvM, 

 Thank you for your reply too. The bit stream we are dealing here is a 311.04Mbps 8B10B encoded bit stream. Do you mind pointing me to the protocol implementation that supports oversampling?  Thanks, Hua

[Altera_Forum]

So to oversample a bit stream of 311.04MHz 5x, I just need to set the transceiver in basic mode, tell the transceiver that the bit stream data rate is 1.5552gbps, and set the PMA-PCS interface width to be 10 bit, this way the output of the transceiver will be 10 bit wide and 155.52MHz data rate, represent 2 bits of the actually data. Then I will write custom code to determine the 2 bit value from the 10 bit and maybe convert it to back to 311.02Mbps bit stream that is synchronized to the local clock, then do the deserializing, 8B10B, etc. 

 Am I on the right track?   Thanks, Hua

[Altera_Forum]

--- Quote Start ---   Thank you for your reply. You are right, Xilinx only do data in this scenario. We have a product using this feature from Xilinx right now, I don't know the details but Xilinx transceiver picks the sample point close to the middle automatically based on statistics.    --- Quote End ---  The Altera parts can probably be configured to do it automatically too. The eyeQ feature of the receiver allows you to control the sampling location for data rates up to 3.5Gbps, so you may want to consider using that to evaluate how well the receiver is selecting the center of the eye pattern.    --- Quote Start ---   Do you mind point me to the Altera documentation you mentioned about using over-sampling to receive data?   --- Quote End ---  Search for over-sampling in the Stratix IV handbook. There is one mention of it under CPRI.    --- Quote Start ---   Is the phase picking process automated on Altera side?   --- Quote End ---  It is in lock-to-data mode for regular data rates. I do not know what it does for over-sampled data rates.    --- Quote Start ---   311.04Mbps 8B10B encoded bit stream   --- Quote End ---  You will not be able to use 8/10B decoding in the receiver hard IP. You will have to decode after you receive the oversampled data into the fabric.  Why not use the LVDS receivers at this data rate?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  So to oversample a bit stream of 311.04MHz 5x, I just need to set the transceiver in basic mode, tell the transceiver that the bit stream data rate is 1.5552gbps, and set the PMA-PCS interface width to be 10 bit, this way the output of the transceiver will be 10 bit wide and 155.52MHz data rate, represent 2 bits of the actually data. Then I will write custom code to determine the 2 bit value from the 10 bit and maybe convert it to back to 311.02Mbps bit stream that is synchronized to the local clock, then do the deserializing, 8B10B, etc.  Am I on the right track?    --- Quote End ---  Yes. You would probably then pack the 2-bit samples into a 10-bit word, and then implement the sync-code detection, word-alignment, 8/10B decode logic implemented in the receiver hard IP block. In fact, for LVDS SERDES this would need to be implemented in the fabric as well, so perhaps there is already code that implements 8/10B alignment and decoding via the fabric, and you can just reuse that code. Seach the Altera app notes.  Modelsim can be used to simulate the receivers. I'd start there.  Cheers, Dave

[Altera_Forum]

Note that the altlvds_rx block has CDR and should run at much lower rates. May be what you're looking for. The 8b/10b would have to be done in logic though.

[Altera_Forum]

--- Quote Start ---  Note that the altlvds_rx block has CDR and should run at much lower rates. May be what you're looking for. The 8b/10b would have to be done in logic though.  --- Quote End ---    Yes! I will look into this. Thanks!:D