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Hi,
I am not very familiar with DDR components and I don’t want to miss anything or make errors in my design. I try to follow the cyclone III dev kit schematic (TPS51100 to generate Vref and Vtt for example) but it uses external terminations and I don't have much place on my board. components : => Cyclone IV EP4CE30 (1 DDR <-> bank 3 & 4 // 1 DDR <-> bank 7 & 8) => 2xDDR2 MT47H32M16-25E fpga side : VCCIO : +1.8V (bank3,4,7,8) - rup2 : 49.9Ohm pull-up to +1.8V / rdn2 : 49.9Ohm pull-down to GND - rup4 : 49.9Ohm pull-up to +1.8V / rdn4 : 49.9Ohm pull-down to GND - point to point connected to DDR2 devices pinout parameters : - IO standard = SSTL 18 class I - output termination = series 50ohm with calibration (dq, dqs) - assignment/timings verified by compilation ddr2 controller parameters (hpc2) : - memory drive strength setting = reduced - memory ODT setting = 50 ohms - memory format = discrete device Do I miss something ? Do I have to connect FPGA Vref IO (VREFBxNy) to DDR Vref (0.9V) ? Do I have to add series resistor on ADDR / command signals and parallel resistor between differential ck/ck_n ? Thanks for helping. SGLink Copied
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--- Quote Start --- Hi, I am not very familiar with DDR components and I don’t want to miss anything or make errors in my design. I try to follow the cyclone III dev kit schematic (TPS51100 to generate Vref and Vtt for example) but it uses external terminations and I don't have much place on my board. components : => Cyclone IV EP4CE30 (1 DDR <-> bank 3 & 4 // 1 DDR <-> bank 7 & 8) => 2xDDR2 MT47H32M16-25E fpga side : VCCIO : +1.8V (bank3,4,7,8) - rup2 : 49.9Ohm pull-up to +1.8V / rdn2 : 49.9Ohm pull-down to GND - rup4 : 49.9Ohm pull-up to +1.8V / rdn4 : 49.9Ohm pull-down to GND - point to point connected to DDR2 devices pinout parameters : - IO standard = SSTL 18 class I - output termination = series 50ohm with calibration (dq, dqs) - assignment/timings verified by compilation ddr2 controller parameters (hpc2) : - memory drive strength setting = reduced - memory ODT setting = 50 ohms - memory format = discrete device Do I miss something ? Do I have to connect FPGA Vref IO (VREFBxNy) to DDR Vref (0.9V) ? Do I have to add series resistor on ADDR / command signals and parallel resistor between differential ck/ck_n ? Thanks for helping. SG --- Quote End --- e-mail me bekrenyov@mail.ru
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