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problems: object "std_logic" is not declared

Altera_Forum
Honored Contributor II
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Hi; 

I try write a code for convert integer to ufixed: 

 

package my_data_types is 

type vector is array (natural range <>) of integer; 

type ufixed is array (natural range <>) of std_logic; 

end my_data_types; 

 

library ieee; 

library ieee_proposed; 

use ieee_proposed.fixed_pkg.all; 

use work.my_data_types.all; 

 

entity fix is 

port (clk: in bit; 

nprev: in vector (0 to 7); 

ip1: out ufixed (3 downto -4)); 

end fix; 

 

architecture fix of fix is 

signal n1: ufixed (3 downto -4); 

begin 

process(clk) 

begin 

if (clk'event and clk='1') then 

for i in 0 to 7 loop 

ip1(i) <= to_ufixed (nprev(i),n1); 

end loop; 

end if; 

end process; 

end fix; 

 

I get this error: 

Error (10482): VHDL error at fix.vhd(3): object "std_logic" is used but not declared. 

 

How to declare the "std_logic" in package?..
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Altera_Forum
Honored Contributor II
1,701 Views

First of all. DO NOT declare your own version of ufixed, it is in the fixed_pkg library. You are going to have problems if you do this. 

 

Secondly, you need to include the line: 

 

library ieee; 

use ieee.std_logic_1164.all;
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Altera_Forum
Honored Contributor II
1,701 Views

What the right way to declare ufixed as an array?..thanks for reply

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Altera_Forum
Honored Contributor II
1,701 Views

you dont need this 

 

type ufixed is array (natural range <>) of std_logic; 

 

It is already declared in the fixed_pkg.
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Altera_Forum
Honored Contributor II
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Now I get this error: 

Error (10511): VHDL Qualified Expression error at fix.vhd(23): to_ufixed type specified in Qualified Expression must match std_ulogic type that is implied for expression by context. 

At this line: ip1(i) <= to_ufixed (nprev(i),n1); 

 

Why?..thanks for reply
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Altera_Forum
Honored Contributor II
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ip1(i) is a single bit. You cannot assign an entire array (the ufixed) to a single bit. 

 

You need to decalre an array of ufixed values.
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Altera_Forum
Honored Contributor II
1,701 Views

Sorry Tricky, I don't get what you say. How to declare an array of ufixed values? Thanks for reply

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Altera_Forum
Honored Contributor II
1,701 Views

type ufixed_array_t is array(natural range <>) of ufixed(3 downto -4); 

 

signal a : ufixed_array_t(0 to 7); 

 

etc
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Altera_Forum
Honored Contributor II
1,701 Views

This is my package code: 

package my_data_types is 

type vector is array (natural range <>) of integer; 

type ufixed_array_t is array (natural range <>) of ufixed (3 downto -4); 

end my_data_types; 

 

But then, error said: 

Error (10482): VHDL error at fix.vhd(3): object "ufixed" is used but not declared 

 

How to avoid this error?..Thanks for reply
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Altera_Forum
Honored Contributor II
1,701 Views

you need to include the fixed_pkg.

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Altera_Forum
Honored Contributor II
1,701 Views

I already include the fixed_pkg..

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Altera_Forum
Honored Contributor II
1,701 Views

you clearly didnt for the package. you have to have separate library imports for each package and entity

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Altera_Forum
Honored Contributor II
1,701 Views

What do you mean by "separate library imports for each package and entity"? 

Thanks for reply
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Altera_Forum
Honored Contributor II
1,701 Views

in your code, you have the package above the library includes. 

 

you need to do this: 

 

--libraries for the package library ieee; use ieee.std_logic_1164.all; library IEEE_Porposed; use IEEE_Proposed.fixed_pkg.all; package my_package is .... end package; --Now the libraries for the entity library ieee; use ieee.std_logic_1164.all; library IEEE_Porposed; use IEEE_Proposed.fixed_pkg.all; use work.my_package.all;  

 

Usually, you would put the package and entity in a separate file.
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Altera_Forum
Honored Contributor II
1,701 Views

Thanks Tricky..I learn a lot from you. I appreciate it.

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Altera_Forum
Honored Contributor II
1,701 Views

May I suggest you read a VHDL tutorial - a lot of the questions you are asking are very very basic.

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Altera_Forum
Honored Contributor II
1,701 Views

Yes, I will. Since now, I still learn form vhdl tutorial and other materials for my better understand.Thanks for the advise =)

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