PCIe design

Altera_Forum · ‎04-29-2017

Hi guys!!

Well, I've got one DSP and one FPGA and I have to communite them by PCIe.

My questions are:

1.- One of them must be a root port (and another one must be endpoint) ??

if this question is true, Which of them do you recomend me to be root port and endpoint?

2.- Can they both are endpoint??

Thanks for reply

Altera_Forum · ‎04-30-2017

There has to be a root complex (RC) in any PCIe system. If the FPGA and DSP core are the only two devices that are on the PCIe bus, then one of them must be the RC, yes.

You haven't stated what your DSP board is. However it is likely that it doesn't have the capability to be the RC - devices are either an endpoint (EP) or the RC, they cannot (?) be both. If your DSP board doesn't have the capability to be an RC, then the FPGA must be configured to perform that task.

The Altera PCIe Hard-IP cores support RC mode so you should be able to set it up. Though be under no illusion that this is a simple task - PCIe is complicated and setting it up requires some effort. There are sample designs that can help, but even those have a steep learning curve.

If you don't want to set up an RC, you could plug both the FPGA and DSP cards into a computer. The computer has an RC built in to the CPU or chipset, which means that both of your devices can then be end points. The computer will do the work of configuring the devices and the PCIe bus, and then once set up the FPGA and DSP can talk to each other autonomously.

Altera_Forum · ‎05-01-2017

Thanks for reply

Well I must use a TMS320C6678 (of Texas Instruments).

I've read its datasheet and I can to programed like a Endpoint or Root Complex.

I've only used the FPGA like endpoint using PCie avalon MM. Now, I just can simulate the communication because I don't have FPGA yet . (Therefore, I've been asking in this forum)

Thanks for tell me kind of PCIe's devices have to use.

Altera_Forum · ‎05-01-2017

In which case use the DSP chip as the RC.

It's far harder to set up a root complex than an endpoint on the FPGA. So you are better off using the DSP chip which has already be set up to act as the RC than to try and spin your own.